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path: root/src/dynarec/arm64_emitter.h (follow)
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* [DYNAREC] Refactored dynarec to ease the future adding of new target ↵ptitSeb2022-02-271-1755/+0
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* [DYNAREC] Small change to unused PRECISE_CVT partptitSeb2022-01-071-0/+4
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* [DYNAREC] Added 66 0F D1 opcode and improved 66 0F D2 opcodeptitSeb2022-01-061-0/+9
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* [DYNAREC] Added DMB emitterptitSeb2021-11-141-0/+3
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* Added AES-NI cpu extension support ([DYNAREC] too, using AES extension if ↵ptitSeb2021-08-281-0/+9
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* Added 64 F7 opcode ([DYNAREC] too) (for #73)ptitSeb2021-07-271-7/+10
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* Added 66 0F C8..CF opcodes ([DYNAREC] too)ptitSeb2021-07-091-2/+4
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* Added 66 0F 38 08/09/0A opcodes ([DYNAREC] too) (for #32 / Zoom)ptitSeb2021-07-051-0/+19
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* Forgot this file from previous commitptitSeb2021-07-051-0/+5
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* [DYNAREC] Small optim on shl/shr 16bits, and marked all opcode that need ↵ptitSeb2021-06-181-0/+9
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* [DYNAREC] Optimized DIV/IDIV 32/64bits opcodesptitSeb2021-06-181-4/+18
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* [DYNAREC] Added shld32c emiter and 0F A4 opcodeptitSeb2021-06-141-0/+2
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* Added 66 0F 3A 0B opcode ([DYNAREC] too)ptitSeb2021-06-141-0/+8
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* Added 0F 0D /1 opcode ([DYNAREC] too)ptitSeb2021-05-281-0/+2
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* [DYNAREC] More emittersptitSeb2021-05-171-10/+37
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* [DYNAREC] Added 0F 64/65/66/6B/72/75/76/D3/F5 opcodesptitSeb2021-04-181-0/+8
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* Second passrajdakin2021-04-141-1/+2
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* [DYNAREC] Added 0F 74 opcodeptitSeb2021-04-111-0/+3
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* [DYNAREC] Added 66 0F E2 ocpodeptitSeb2021-04-111-0/+25
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* [DYNAREC] Added DF opcodesptitSeb2021-04-031-11/+44
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* [DYNAREC] Added DB opcodesptitSeb2021-04-031-4/+19
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* [DYNAREC] Added D9 opcodesptitSeb2021-04-031-0/+15
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* [DYNAREC] Added F3 0F 52 opcodeptitSeb2021-04-031-0/+15
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* [DYNAREC] Added 0F 73 opcodeptitSeb2021-04-021-0/+10
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* Added 66 0F 38 0B opcode ([DYNAREC] too)ptitSeb2021-04-021-0/+15
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* Added 0F E0 opcode ([DYNAREC] too)ptitSeb2021-04-021-0/+29
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* [DYNAREC] Fixed SQXTUN2_8 emiter, and so 66 0F 67 opcodeptitSeb2021-04-021-8/+6
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* [DYNAREC] Fixed 67 8D opcde, and remove hack for 67 REX.W, it was wrongptitSeb2021-04-011-0/+1
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* [DYNAREC] Added 66 0F F5 opcodeptitSeb2021-04-011-7/+7
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* [DYNAREC] Added 0F 70 opcodeptitSeb2021-03-311-0/+1
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* [DYNAREC] Added 66 0F E5 opcodeptitSeb2021-03-311-0/+6
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* [DYNAREC] Added 66 0F DC/DD/DE opcodesptitSeb2021-03-311-0/+35
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* [DYNAREC] Added 66 0F D8/D9 opcodesptitSeb2021-03-311-0/+19
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* [DYNAREC] Add 66 0F E4 opcodeptitSeb2021-03-311-0/+15
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* [DYNAREC] Added 0F 67/71 opcodesptitSeb2021-03-311-1/+1
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* [DYNAREC] Added 66 0F EC/ED opcodesptitSeb2021-03-311-0/+19
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* [DYNAREC] Added 66 0F 38 04 opcodeptitSeb2021-03-311-0/+52
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* [DYNAREC] Added 66 0F 38 00 and fixed 66 0F 67 opcodesptitSeb2021-03-311-0/+5
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* [DYNAREC] Added 66 0F 67 opcodeptitSeb2021-03-311-7/+23
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* [DYNAREC] Added F2 0F 70 opcodeptitSeb2021-03-311-0/+1
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* [DYNAREC] Added 66 0F F6 opcodeptitSeb2021-03-311-0/+73
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* [DYNAREC] Fixed PLD emitter, fixing 0F 18 opcode for good this timeptitSeb2021-03-301-1/+1
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* [DYNAREC] Optimized a bit 66 0F 70 opcodeptitSeb2021-03-301-4/+4
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* [DYNAREC] Fixed 0F 18 opcodesptitSeb2021-03-291-6/+6
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* [DYNAREC] Added 0F C2 opcodeptitSeb2021-03-291-0/+19
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* [DYNAREC] Added 0F 18 opcodesptitSeb2021-03-281-0/+18
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* [DYNAREC] Added F0 C7 opcodeptitSeb2021-03-281-0/+8
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* [DYNAREC] Added F2 0F 2D opcodes, and use a simpler version of the ↵ptitSeb2021-03-241-0/+12
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* [DYNAREC] Refined 66 0F 5B with a switch for the rounding modeptitSeb2021-03-241-1/+6
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* [DYNAREC] Added 64 C7 opcodeptitSeb2021-03-241-0/+1
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