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* [DYNACACHE][RV64] Enabled dynacache for RV64 (#2762)Yang Liu2025-06-201-15/+15
* [DYNACACHE][RV64] More work on internal reloc (#2759)Yang Liu2025-06-191-61/+61
* [DYNACACHE] Refactored cpu extension, will be used in dynacache signature checksptitSeb2025-06-141-121/+121
* [RV64_DYNAREC] Fixed regression introduced in #2669 (#2676)Yang Liu2025-05-271-1/+1
* [RV64_DYNAREC] Improved ret_to_epilog with xtheadmemidx (#2670)Yang Liu2025-05-261-1/+5
* [RV64_DYNAREC] Minor nativeflags optim to LEA and CMOVcc opcodes (#2669)Yang Liu2025-05-261-0/+42
* [RV64_DYNAREC] Optimized CLZ macro with xtheadbb (#2664)Yang Liu2025-05-231-38/+46
* [RV64_DYNAREC] Optimized some opcodes with xtheadbb (#2663)Yang Liu2025-05-231-13/+17
* [RV64_DYNAREC] Improved POPCNT and fixed some scratch conflicts (#2651)Yang Liu2025-05-201-2/+2
* [RV64_DYNAREC] Enabled native flags optimization for SETcc opcodes (#2640)Yang Liu2025-05-161-0/+51
* [RV64_DYNAREC] Fixed x87 cache swapping (#2571)Yang Liu2025-04-241-0/+8
* [RV64_DYNAREC] Fixed some x87 rounding cases for fastround=0 (#2437)Yang Liu2025-03-131-12/+12
* [RV64_DYNAREC] Added a fast path to SHR Ew, Ib (#2188)Yang Liu2024-12-221-3/+3
* [RV64_DYNAREC] Fixed 32bits SUBz (#2170)Yang Liu2024-12-181-1/+9
* [RV64_DYNAREC] Fixed 32bit ADDIz (#2168)Yang Liu2024-12-181-1/+9
* [RV64_DYNAREC] Optimize push/pop with xtheadmemidx (#2150)Yang Liu2024-12-131-28/+98
* [RV64_DYNAREC] Reworked ZEROUP and freed t0 (#2147)xctan2024-12-121-7/+18
* [RV64_DYNAREC] New register mapping (#2139)Yang Liu2024-12-121-80/+4
* [DYNAREC] Introduced TO_NAT to ease register mapping changes in future (#2111)Yang Liu2024-12-051-115/+114
* [RV64_DYNAREC] Added simple opcodes fusion as "native flags" (#2102)Yang Liu2024-12-021-5/+41
* [DYNAREC] Reuse strongmem infra for all backends (#2052)Yang Liu2024-11-211-0/+6
* [DYNAREC] Reworked strong memory emulation (#2043)Yang Liu2024-11-191-1/+1
* [RV64_DYNAREC] Prefer AMO* instructions over LR/SC when possible (#2028)Yang Liu2024-11-131-0/+26
* [RV64_DYNAREC] Added more opcodes for vector (#1987)Yang Liu2024-10-311-0/+3
* [RV64_DYNAREC] Fixed more issues for vector (#1928)Yang Liu2024-10-121-2/+2
* [DYNAREC] Tweaking indirect jumps for CALL/RET to use the return address stac...Yang Liu2024-10-061-2/+2
* [RV64_DYNAREC] Added more opcodes for xtheadvector and fixed more issues (#1897)Yang Liu2024-10-031-1/+2
* [RV64_DYNAREC] Added preliminary xtheadvector support (#1892)Yang Liu2024-10-021-46/+70
* [RV64_DYNAREC] Refined RISC-V vector emitter (#1884)Yang Liu2024-09-291-295/+293
* [RV64_DYNAREC][BOX32] Improved some 66 prefix opcodes (#1865)Yang Liu2024-09-241-0/+5
* [RV64_DYNAREC] Added 1 more opcode for vector and some refactor and fixes too...Yang Liu2024-09-131-26/+31
* [RV64_DYNAREC] Optimized jump_to_next using XTheadBb instructions (#1768)Yang Liu2024-08-281-2/+2
* [BOX32][RV64_DYNAREC] Fixed more issues and enable CI for box32 (#1767)Yang Liu2024-08-281-1/+9
* [BOX32][RV64_DYNAREC] Added preliminary box32 support to RV64 (#1766)Yang Liu2024-08-281-5/+5
* [RV64_DYNAREC] Fix some typos in docs and dynarec/rv64 (#1758)WANG Guidong2024-08-261-7/+7
* [RV64_DYNAREC] Fixed more issues in the vector infrastructure (#1755)Yang Liu2024-08-251-2/+2
* [RV64_DYNAREC] Added 66 0F 3A 63 PCMPISTRI opcode (#1735)Yang Liu2024-08-161-5/+5
* [RV64_DYNAREC] Fixed vector infra (#1705)Yang Liu2024-07-221-0/+3
* [RV64_DYNAREC] Added more 66 0F 38 opcodes for vector (#1699)Yang Liu2024-07-191-0/+2
* [RV64_DYNAREC] Added vector SEW cache (#1698)Yang Liu2024-07-191-0/+2
* Fixes (#1659)rajdakin2024-07-091-92/+92
* Mask `rs2` when using `bext` instruction if `rex.w` is not set (#1653)Yip Coekjan2024-07-081-4/+9
* [RV64_DYNAREC] Added preliminary RVV infra and PXOR opcode for demonstration ...Yang Liu2024-07-041-0/+17
* [RV64_DYNAREC] Added vector instructions emitter (#1621)Yang Liu2024-06-271-79/+533
* [RV64_DYNAREC] Fixed potential issue of jump_to_next (#1600)Yang Liu2024-06-181-0/+2
* [RV64_DYNAREC] Added more MMX opcodes and some optimizations too (#1535)xctan2024-05-281-1/+9
* [RV64_DYNAREC] Fixed some issue with shld/shrd emitterptitSeb2024-05-201-6/+6
* [DYNAREC][32BITS] Fixed and improved 66 prefix opcodes (#1485)Yang Liu2024-05-021-0/+12
* [DYNAREC] Fixed shift xw macros (#1443)Yang Liu2024-04-141-7/+24
* [RV64_DYNAREC] Added 66 0F 38 61 PCMPESTRI opcode and some refactors too (#1337)Yang Liu2024-03-061-2/+59