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* [ARM64_DYNAREC] Add a test about arm64 addresses in pass3, and abort if wrongptitSeb2024-07-211-0/+1
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* [DYNAREC] Fixed a typo in an error messageptitSeb2024-07-211-2/+2
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* [LA64_DYNAREC] Added more opcodes (#1701)Yang Liu2024-07-205-722/+811
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* [LA64_DYNAREC] Added more opcodes (#1700)Yang Liu2024-07-205-0/+131
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* [RV64_DYNAREC] Added more 66 0F 38 opcodes for vector (#1699)Yang Liu2024-07-192-0/+34
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* [RV64_DYNAREC] Added vector SEW cache (#1698)Yang Liu2024-07-1915-76/+143
| | | | | * [RV64_DYNAREC] Added vector SEW cache * handling reset_n
* [RV64_DYNAREC] Added 66 0F 38 00 PSHUFB for vector (#1697)Yang Liu2024-07-183-4/+32
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* [RV64_DYNAREC] Added more 66 0F opcodes for vector (#1696)Yang Liu2024-07-182-0/+47
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* [RV64_DYNAREC] Show missing opcodes in vector implementation (#1695)Yang Liu2024-07-183-3/+22
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* [LA64_DYNAREC] Added more opcodes and fixed more issues (#1692)Yang Liu2024-07-174-6/+90
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* [LA64_DYNAREC] Added more opcodes (#1690)Yang Liu2024-07-172-3/+95
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* [LA64_DYNAREC] Added more opcodes (#1688)Yang Liu2024-07-163-0/+90
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* [LA64_DYNAREC] Fixed CMPSD (#1687)Yang Liu2024-07-161-1/+1
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* [LA64_DYNAREC] Fixed some opcodes (#1686)Yang Liu2024-07-162-3/+9
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* [RV64_DYNAREC] Fixed GETGXSS_empty on upper bits handling (#1685)Yang Liu2024-07-161-2/+1
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* [RV64_DYNAREC] Clear high 32bits when write back as single (#1684)Yang Liu2024-07-161-2/+5
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* [LA64_DYNAREC] Remove xMASK and fixed 86 XCHG opcode (#1683)Yang Liu2024-07-1613-90/+67
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* [ARM64_DYNAREC] Fixed OR Ew, Gw (#1682)Yang Liu2024-07-161-1/+1
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* [RV64_DYNAREC] Fixed some bugs for VMP (#1679)xctan2024-07-165-49/+41
| | | | | | | * [RV64_DYNAREC] Fixed reg x3 conflict with the GETEW macro * [RV64_DYNAREC] Fixed (LOCK) XCHG Eb, Gb again * [RV64_DYNAREC] Fixed register conflict in (LOCK) XCHG Eb, Gb
* [LA64_DYNAREC] Added 2 more opcodes (#1680)Yang Liu2024-07-152-0/+21
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* [RV64_DYNAREC] Cleanup for removed rv64_lock_cas_dq (#1670)Ivan Melnikov2024-07-112-4/+0
| | | | | | | | Since rv64_lock_cas_dq is removed, we should also remove its global symbol declaration and its prototype. Otherwise, we get and undefined symbol reference, which breaks ELF checks that some distros employ. Fixes: 9dbd7fc7e0615f48c9287305610bf9aed1cc24f3
* [ARM64_DYNAREC] Added handling of FASTNAN=0 to MULSS opcodeptitSeb2024-07-111-4/+17
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* fix some spelling (#1668)josch2024-07-1010-24/+24
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* [DYNAREC] Fixed `ymm0_purge` for some instructions (#1664)rajdakin2024-07-101-2/+6
| | | | | * [DYNAREC] Fixed `ymm0_purge` for the first instruction of a block * [DYNAREC] Also consider barriers as having a pred with `ymm0_out = 0`
* Remove the flags adjustment in `GO_TRACE` for RISC-V 64 (#1663)Yip Coekjan2024-07-101-3/+1
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* [LA64_DYNAREC] Added more opcodes and a minor fix too (#1662)Yang Liu2024-07-103-1/+97
| | | | | * [LA64_DYNAREC] Added more opcodes and a minor fix too * saturation is considered necessary
* Fixes (#1659)rajdakin2024-07-0926-275/+279
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Replaced some tabs with spaces * Fixed some signedness warnings * Added more debug info * Fixed an improper alignment * [WRAPPEDWAYLAND] Added return statements to wrappers * [EMU] [AVX] Fixed some issues * [ARM DYNAREC] Fixed some minor warnings * [ARM DYNAREC] Removed unused macro arguments * [EMU] Fixed a noisy warning * [ARM DYNAREC] Removed "empty body" warnings * [EMU] Fixed an opcode in dynarec, non-cosim builds * [LA64 DYNAREC] Minor warning fixes * [LA64 DYNAREC] Fixed empty body warnings * [LA64 DYNAREC] Added parenthesis around assignments in if statements * [LA64 DYNAREC] Fixed missing parenthesis in macro definitions * [RV64 DYNAREC] Fixed minor warnings * [RV64 DYNAREC] Fixed wrong/missing parentheses * [WRAPPER] Fixed the WaylandClient callback signatures
* [LA64_DYNAREC] Fixed ADC/SBC usage (#1658)Yang Liu2024-07-081-5/+5
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* [ARM64_DYNAREC] Small optim on some ROL/ROR opcodesptitSeb2024-07-081-30/+46
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* [LA64_DYNAREC] Added more opcodes (#1656)Yang Liu2024-07-081-0/+33
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* [LA64_DYNAREC] Added more opcodes (#1654)Yang Liu2024-07-084-0/+145
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* Mask `rs2` when using `bext` instruction if `rex.w` is not set (#1653)Yip Coekjan2024-07-082-7/+17
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* Set last_ip to an unclean state at the end of CALL (#1650)Yang Liu2024-07-071-0/+1
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* [ARM64_DYNAREC] Fixed a warningptitSeb2024-07-071-1/+1
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* [ARM64_DYNAREC] Added AVX.66.0F38 B6 opcodeptitSeb2024-07-071-0/+27
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* [ARM64_DYNAREC] Added AVX.F2.0F D0 opcodeptitSeb2024-07-071-0/+21
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* [ARM64_DYNAREC] Fixed reflect cache for ymm0ptitSeb2024-07-071-1/+2
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* [ARM64_DYNAREC] Reworked ymm0 propagationptitSeb2024-07-0710-50/+82
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* [ARM64_DYNAREC] More improvment on YMM handlingptitSeb2024-07-056-24/+39
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* [ARM64_DYNAREC] Added Calling Convention as comment in emitter, for referenceptitSeb2024-07-051-0/+35
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* [ARM64_DYNAREC] Improved 0F C7 /6 opcodeptitSeb2024-07-041-2/+23
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* [DYNAREC] Fixed IMUL sign extension issue (#1639)Yang Liu2024-07-045-34/+26
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* [LA64_DYNAREC] Fixed F2 0F 70 PSHUFLW opcode (#1634)Yang Liu2024-07-041-1/+8
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* [RV64_DYNAREC] Added preliminary RVV infra and PXOR opcode for demonstration ↵Yang Liu2024-07-049-92/+416
| | | | | | | | | | | | | (#1632) * [RV64_DYNAREC] Added preliminary RVV infra and PXOR opcode for demonstration * keep sse_cache_s uint8_t as suggested * use xor to do the wrap * revert * better fallback
* [RV64_DYNAREC] modify DF default /4 opcode (#1633)LiZhuoheng2024-07-041-5/+14
| | | | | * [RV64_DYNAREC] modify DF default /4 opcode * [RV64_DYNAREC] added DF default /4 opcode
* [RV64_DYNAREC] Added DF default /4 opcode (#1631)LiZhuoheng2024-07-031-0/+27
| | | | | * [RV64_DYNAREC] Added DF default /4 opcode * replace tabs to spaces
* Add missing func declarations: `get_first_jump_addr` (#1627)Yip Coekjan2024-07-022-0/+2
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* [DYNAREC] Improved cache coherency and internal jump handling, ↵ptitSeb2024-07-025-4/+52
| | | | [ARM64_DYNAREC] Improved YMM register tracking
* [DYNAREC] Reset fpu scratch after Instruction epilogptitSeb2024-07-011-2/+1
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* [DYNAREC] Keep internal jmp table to the endptitSeb2024-07-011-3/+4
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