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* [DYNAREC] Somme fix for 66 83 opcodesptitSeb2021-09-261-10/+10
* More work on gtk and nss3+friendsptitSeb2021-09-212-4/+7
* Added 66 0F 38 39/3C opcodes ([DYNAREC] too) (for #81)ptitSeb2021-09-181-0/+16
* Fixed 66 0F 3A 22 opcode for REX.W ([DYNAREC] too) (should help #81)ptitSeb2021-09-161-1/+5
* [DYNAREC] some fixes to alternate handling and vsyscall supportptitSeb2021-09-122-5/+17
* [DYNAREC] Fixed (agaim) BTR/BTS/BTC with imm8==0ptitSeb2021-09-041-0/+6
* Added 66 0F 3A 22 SSE4.x opcode ([DYNAREC] too) (for #106)ptitSeb2021-08-301-0/+10
* [DYNAREC] Fixed BTS/BTR/BTC with imm8==0 (helps EWJ SE Win95, probably other ...ptitSeb2021-08-291-6/+15
* Added 66 0F B7 opcode ([DYNAREC] too)ptitSeb2021-08-291-0/+14
* Added AES-NI cpu extension support ([DYNAREC] too, using AES extension if ava...ptitSeb2021-08-287-0/+263
* [DYNAREC] Added 65 39 opcodeptitSeb2021-08-101-0/+10
* Added handling of longjmp inside signals handler (from box86)ptitSeb2021-08-091-1/+2
* Added 64 66 89 and changed 64 66 0F D6 opcodes ([DYNAREC] too) (for #77)ptitSeb2021-07-302-1/+54
* [DYNAREC] Try toavoid segfault when exploring code for a native call building...ptitSeb2021-07-281-1/+1
* Added 64 F7 opcode ([DYNAREC] too) (for #73)ptitSeb2021-07-273-9/+164
* Fixed status of C2 x87 flags after sin, cos, sincos and tan function ([DYNARE...ptitSeb2021-07-211-0/+4
* Added F3 0F BD opcode ([DYNAREC] too) (for #27)ptitSeb2021-07-191-0/+14
* Made IRETQ to restore RSP and SS ([DYNAREC] too) (helps Wine64 exceptions han...ptitSeb2021-07-171-0/+8
* [DYNAREC] Try to avoid segfault when discovering natuve function durring buil...ptitSeb2021-07-171-1/+2
* [DYNAREC] Added 8F opcode and improved 8C oneptitSeb2021-07-171-3/+20
* [DYNAREC] Fixed P flag computation for Test32 emiter (help #34)ptitSeb2021-07-141-1/+1
* [DYNAREC] Fixed shrd/shld emiter when both regs are the same (for #33)ptitSeb2021-07-121-4/+4
* Added some more libc wrapped functionsptitSeb2021-07-121-1/+1
* Splitted mmx and x87 register (from box86)ptitSeb2021-07-112-16/+16
* [DYNAREC] Stop building block if protection of next byte is 0 without the Cus...ptitSeb2021-07-101-1/+1
* Added 67 E8 opcode ([DYNAREC] too) (for #45)ptitSeb2021-07-101-0/+3
* Added 66 90-97 opcodes ([DYNAREC] too) (for #44)ptitSeb2021-07-091-2/+17
* [DYNAREC] Fixed emiter for shr32c, sar32c and shrd32c (for #44)ptitSeb2021-07-091-3/+9
* Added dummy 36 prefix ([DYNAREC] too) (for #44)ptitSeb2021-07-091-0/+3
* Added 66 0F C8..CF opcodes ([DYNAREC] too)ptitSeb2021-07-092-2/+22
* [DYNAREC] Fixed 66 REX.W opcodesptitSeb2021-07-091-1/+1
* [DYNAREC] Added 66 0F D2 opcodes (for geekbench5)ptitSeb2021-07-081-0/+12
* [DYNAREC] Added 66 0F EE opcodes (for geekbench5)ptitSeb2021-07-081-1/+7
* [DYNAREC] Added 64 FF opcodes (for geekbench5)ptitSeb2021-07-082-0/+67
* [DYNAREC] Better handling of SHL/SHR/SAR Eb, 0 (for obfuscated code)ptitSeb2021-07-071-27/+39
* Added dummy 0F 09 opcode ([DYNAREC] too) (for #34)ptitSeb2021-07-071-0/+4
* [DYNAREC] Fixed FISTP i64 (help #14)ptitSeb2021-07-072-3/+4
* [DYNAREC] Added Need optim message to FINITptitSeb2021-07-071-0/+1
* Added 0F D7 opcode ([DYNAREC] too) (for #32)ptitSeb2021-07-061-1/+17
* Work on CMPSS and CMPSD ([DYNAREC] too)ptitSeb2021-07-062-12/+10
* [DYNAREC] Added 66 0F 50 opcode, and changed a bit 66 0F D7 (for CB15)ptitSeb2021-07-061-24/+32
* [DYNAREC] Added F3 0F 53 opcode (for CB15)ptitSeb2021-07-061-3/+14
* Added 66 0F 38 08/09/0A opcodes ([DYNAREC] too) (for #32 / Zoom)ptitSeb2021-07-052-0/+64
* [DYNAREC] Added 66 0F 5E opcode (for CB15)ptitSeb2021-07-051-1/+7
* [DYNAREC] Added F0 09 opcode (for CB15)ptitSeb2021-07-051-0/+18
* [DYNAREC] Added 66 0F C2 opcode (for CB15)ptitSeb2021-07-051-0/+32
* Added 66 0F 38 1C/1D/1E opcodes ([DYNAREC] too) (for #17 / Zoom)ptitSeb2021-07-051-0/+25
* Added F0 80 opcode ([DYNAREC] too)ptitSeb2021-07-051-1/+162
* [DYNAREC] Added 66 0F D7 opcode (for CB15)ptitSeb2021-07-051-2/+28
* [DYNAREC] Added a faked 0F 01 opcode to avoid break of dynarec blockptitSeb2021-07-051-0/+10