about summary refs log tree commit diff stats
path: root/src/dynarec (follow)
Commit message (Expand)AuthorAgeFilesLines
* [ARM64_DYNAREC] Improved IRET handling of boggus parametersptitSeb2025-09-295-18/+44
* [RV64_DYNAREC] Added more scalar avx opcodes (#3037)Yang Liu2025-09-293-3/+419
* [RV64_DYNAREC] Fixed a scratch register confliction (#3033)Yang Liu2025-09-271-1/+1
* [ARM64_DYNAREC] Added more variant of INS/OUT opcodesptitSeb2025-09-242-1/+77
* [ARM64_DYNAREC] Fixed flags for 8bits imulptitSeb2025-09-241-2/+3
* RV64_DYNAREC] Added more avx scalar opcodes (#3029)Yang Liu2025-09-223-2/+58
* [RV64_DYNAREC] Added more avx scalar opcodes (#3028)Yang Liu2025-09-221-0/+93
* [LA64_DYNAREC] Refactor register mapping (#2940)Leslie Zhai2025-09-1916-248/+317
* [ARM64_DYNAREC] Temporarily disable Atomic path for F0 0F B1, as it avoid som...ptitSeb2025-09-171-2/+5
* [LA64_DYNAREC] Fixed AVX 0F 17 VMOVHPS opcode (#3025)Yang Liu2025-09-171-1/+1
* [ARM64_DYNAREC] Fixed non-Atomic path for F0 0F C0 opcodeptitSeb2025-09-171-4/+4
* [LA64_DYNAREC] Fixed AVX 66 0F 67 PACKUSWB opcode (#3024)Yang Liu2025-09-171-1/+1
* [LA64_DYNAREC] Fixed avx infra (#3023)Yang Liu2025-09-171-2/+2
* [DYNAREC] Improved Memory Barrier handling for LOCK prefixed opcodesptitSeb2025-09-1613-172/+6
* [ARM64_DYNAREC] Allow use of Native flags when using UFLAG_IF macro helperptitSeb2025-09-152-0/+6
* [DYNAREC][TRACE] Show if will run Inter or Dynarec when using LongJump to res...ptitSeb2025-09-141-1/+1
* [DYNAREC] Small refactor on StrongMem emulator and lock prefixptitSeb2025-09-138-12/+8
* [RV64_DYNAREC] Added more scalar avx cmp opcodes (#3016)Yang Liu2025-09-112-0/+160
* [DYNAREC] Fully trust volatile metadata when they are present (fixes Starfiel...ptitSeb2025-09-091-2/+2
* [RV64_DYNAREC] Added more scalar avx opcodes (#3010)Yang Liu2025-09-092-0/+227
* [RV64_DYNAREC] Added more scalar avx opcodes and fixed a typo (#3009)Yang Liu2025-09-082-1/+40
* [ARM64_DYNAREC] A few minor fixes to some opcodesptitSeb2025-09-085-31/+26
* [ARM64_DYNAREC] Added some more UD handling in 64bits dynarecptitSeb2025-09-041-17/+167
* [RV64_DYNAREC] Added more scalar avx opcodes (#3005)Yang Liu2025-09-041-0/+129
* [DYNAREC] Better handling of 32bits 2E & 36 prefix (silent some false negativ...ptitSeb2025-09-031-2/+6
* [DYNAREC] Use a static array for preds temporary, like all the other dynarec ...ptitSeb2025-09-031-7/+4
* [RV64_DYNAREC] Added 1 more scalar avx 0F opcode (#2994)Yang Liu2025-09-011-0/+47
* [RV64_DYNAREC] Added more scalar avx 0F opcodes (#2992)Yang Liu2025-09-012-4/+198
* [INTERP][DYNAREC] Aligned !fastnan handling of 0F 51/52 opcodes (#2989)Yang Liu2025-09-013-15/+52
* [LA64_DYNAREC] Fixed a typo in 0F 53 RCPPS opcode (#2991)Yang Liu2025-09-011-4/+3
* [LA64_DYNAREC] Fix 0f.A3 BT opcode, fix ALSL operand order. (#2988)phorcys2025-09-011-1/+1
* [ARM64_DYNAREC][TRACE] Fixed SWP B/H opcodes printerptitSeb2025-08-311-2/+2
* [ARM64_DYNAREC] Introduced a dynarec version of the UpdateFlags helper functionptitSeb2025-08-3014-26/+1183
* Fixed a misguarded box32 endif (#2982)Yang Liu2025-08-301-1/+1
* [RV64_DYNAREC] Added more scalar avx opcodes (#2980)Yang Liu2025-08-301-0/+270
* [LA64_DYNAREC] Fixed AVX VCVT[T]PS2DQ fastround path (#2979)Yang Liu2025-08-293-11/+19
* [RV64_DYNAREC] Added more scalar avx opcodes (#2978)Yang Liu2025-08-292-1/+179
* Improved handling of TF flagptitSeb2025-08-271-2/+7
* [RV64_DYNAREC] Added more scalar avx opcodes (#2975)Yang Liu2025-08-274-67/+176
* [RV64_DYNAREC] Added more scalar avx opcodes (#2974)Yang Liu2025-08-261-0/+601
* [RV64_DYNAREC] Added more scalar avx opcodes (#2973)Yang Liu2025-08-261-0/+97
* [RV64_DYNAREC] Added more scalar avx opcodes (#2971)Yang Liu2025-08-253-4/+571
* [RV64_DYNAREC] Added more scalar avx opcodes (#2970)Yang Liu2025-08-251-0/+171
* [RV64_DYNAREC] Added YMM0 placeholder for later optim (#2968)Yang Liu2025-08-247-241/+125
* [RV64_DYNAREC] Fixed scalar avx VCMPPD non-ymm case (#2966)Yang Liu2025-08-221-0/+4
* [RV64_DYNAREC] Added more scalar avx opcodes (#2965)Yang Liu2025-08-222-0/+516
* [ARM64_DYNAREC] Fixed an inst name typo (#2964)Yang Liu2025-08-221-1/+5
* [RV64_DYNAREC] Added scalar SSE 66 0F 3A 60/61/62 opcodes (#2963)Yang Liu2025-08-222-1/+123
* [RV64_DYNAREC] Added more scalar avx 66 0F opcodes (#2960)Yang Liu2025-08-222-1/+226
* [RV64_DYNAREC] Added more scalar avx opcodes (#2961)Yang Liu2025-08-215-1/+105