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* [LA64_DYNAREC] Fix VMOVNTDQA. (#2934)phorcys2025-08-152-16/+16
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* [LA64_DYNAREC] Add la64 avx insts using helpers. (#2935)phorcys2025-08-152-22/+168
| | | | VEX.66.0F.38 VAESIMC, VAESENC, VAESENCLAST, VAESDEC, VAESDECLAST VEX.66.0F.3a VPCLMULQDQ, VAESKEYGENASSIST
* [RV64_DYNAREC] Removed a dispensable line from dump (#2932)Yang Liu2025-08-133-10/+0
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* [LA64_DYNAREC] Fixed a typo in CMPXCHG8B opcode (#2931)Yang Liu2025-08-131-1/+1
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* [DYNAREC] Rearranged arch-specific AVX infra code (#2930)Yang Liu2025-08-1314-324/+131
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* [LA64_DYNAREC] Fix B3 BTR eflags when cpuext.lbt == 1. Fix 16bits AND when ↵phorcys2025-08-122-2/+6
| | | | cpuext.lbt == 1. (#2929)
* [RV64_DYNAREC] Added F0 08 LOCK OR opcode (#2928)Yang Liu2025-08-121-0/+25
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* [RV64_DYNAREC] Fixed F0 10 LOCK ADC opcode (#2927)Yang Liu2025-08-111-4/+7
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* [RV64_DYNAREC][LA64_DYNAREC] Fixed missing zeroup in geted_32() (#2921)Yang Liu2025-08-082-0/+2
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* [LA64_DYNAREC] Fixed AVX VPMOVMSKB opcode (#2920)Yang Liu2025-08-071-2/+2
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* [LA64_DYNAREC] Fixed AVX VPERM2F128/VPERM2I128 opcodes (#2919)Yang Liu2025-08-071-1/+1
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* [LA64_DYNAREC] Fixed AVX VMASKMOVDQU opcode (#2918)Yang Liu2025-08-071-1/+1
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* [LA64_DYNAREC] Fixed AVX VPBLENDW opcodes (#2917)Yang Liu2025-08-071-18/+6
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* [LA64_DYNAREC] Fixed AVX VMOVMSKPS/VMOVMSKPD opcodes (#2916)Yang Liu2025-08-072-4/+4
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* [LA64_DYNAREC] Fixed AVX VMOVSS opcode (#2915)Yang Liu2025-08-071-1/+1
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* [LA64_DYNAREC] Fixed AVX VCMPSS/VCMPSD opcodes (#2914)Yang Liu2025-08-072-2/+4
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* [LA64_DYNAREC] Fixed some AVX scalar MIN/MAX opcodes (#2913)Yang Liu2025-08-072-5/+5
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* [LA64_DYNAREC] Refined F3 0F 5D/5F MINSS/MAXSS opcodes (#2912)Yang Liu2025-08-071-18/+16
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* [ARM64_DYNAREC] Fixed AVX VMOVMSKPD opcode (#2909)Yang Liu2025-08-061-2/+2
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* [ARM64_DYNAREC] Fixed AVX VMOVSS opcode (#2908)Yang Liu2025-08-061-1/+1
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* [ARM64_DYNAREC][INTERP] Fixed AVX VPERM2F128/VPERM2I128 opcodes (#2907)Yang Liu2025-08-061-4/+4
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* [LA64_DYNAREC] Fixed 66 0F 3A 16 PEXTRD opcode (#2906)Yang Liu2025-08-061-1/+1
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* [LA64_DYNAREC] Fixed 66 F3 0F B8 POPCNT opcode (#2905)Yang Liu2025-08-061-4/+5
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* [RV64_DYNAREC] Added 1 more opcode (#2903)Yang Liu2025-08-062-1/+6
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* [LA64_DYNAREC] Added more opcodes (#2902)Yang Liu2025-08-066-1/+248
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* [LA64_DYNAREC] Fixed F3 0F 53 RCPSS opcode (#2892)Yang Liu2025-08-041-7/+3
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* [LA64_DYNAREC] Fixed 66 0F 3A 0F PALIGNR for case where dst==src (#2894)Yang Liu2025-08-041-1/+1
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* [LA64_DYNAREC] Fixed 66 0F 38 06 PHSUBD opcode (#2893)Yang Liu2025-08-041-1/+1
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* [LA64_DYNAREC] Fixed 66 0F 3A 21 INSERTPS opcode (#2891)Yang Liu2025-08-041-6/+4
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* [LA64_DYNAREC] Added and optimized more fastround=0 cases (#2890)Yang Liu2025-08-042-15/+32
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* [LA64_DYNAREC] Fix some la64 ops. (#2889)phorcys2025-08-044-14/+32
| | | | | Fix 0F.BA./7 BTS CF when cpuext.lbt == 1 Fix 66.0F.CF BSWAP 16bits ops. Fix VEXTRACTF128, VINSERTF128
* [LA64_DYNAREC] Fixed 66 0F 38 14 BLENDVPS opcode (#2888)Yang Liu2025-08-041-1/+1
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* [LA64_DYNAREC] Fixed 66 0F 3A 0C/0D BLENDPS/D opcodes (#2887)Yang Liu2025-08-041-2/+2
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* [LA64_DYNAREC] Fixed a few GETEX usage (#2886)Yang Liu2025-08-043-44/+44
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* [LA64_DYNAREC] Fixed 0F E2 PSRAD opcode (#2885)Yang Liu2025-08-041-3/+3
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* [LA64_DYNAREC] Fixed 0F E3 PAVGW opcode (#2884)Yang Liu2025-08-041-1/+1
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* [LA64_DYNAREC] Add la64 avx bit ops. (#2873)phorcys2025-08-044-0/+133
| | | | | | * VEX.66.0F.3A VPEXTRB/VPEXTRW/VPEXTRD/VPEXTRQ VPINSRB/VPINSRD/VPINSRQ * VEX.66.0F.C5 VPEXTRW * VEX.66.0f.C4 VPINSRW * VEX.66.0F.38.41 VPHMINPOSUW
* [LA64_DYNAREC] Fix some la64 avx/sse ops. (#2882)phorcys2025-08-026-37/+80
| | | | | | | | | | | | Fix 66.0F.F3 PSLLQ Fix VEX.66.0F.7E VMOVD not zero-extend Fix Vex.66.0F.3A.06 VPERM2F128/VPERM2I128 Fix Vex.66.0F.3A.0D VBLENDPD Fix VEX.66.0F.3A.18/38 VINSERTF128/VINSERTI128 when q0 == q1 or q0 == q2 Fix VEX.66.0F.3A.21 VINSERTPS fix u8 get pos Fix VEX.66.0F.3A.40 VDPPS Fix VREPLVEIxy emit when vex.l Fix VEX.66.0F.38.0C VPERMILPS Fix VEX.66.0F.38.2B VPACKUSDW Fix VEX.66.0F.38.93 VGATHERQPD
* [RV64_DYNAREC] Fixed scalar version of 66 0F 3A 21 INSERTPS opcode (#2881)Yang Liu2025-08-021-1/+1
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* [RV64_DYNAREC] Fixed scalar and vector versions of mmx PSRAW/PSRAD (#2880)Yang Liu2025-08-022-3/+3
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* [RV64_DYNAREC] Fixed some mmx opcodes (#2879)Yang Liu2025-08-022-7/+13
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* [ARM64_DYNAREC] Fixed PCMPESTRI fastpath SF flag computation (#2876)Yang Liu2025-08-011-5/+5
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* [ARM64_DYNAREC] Fixed a typo (#2875)Yang Liu2025-08-011-1/+1
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* [ARM64_DYNAREC] Fixed some edge cases for mmx PSRLQ (#2874)Yang Liu2025-08-011-1/+3
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* [LA64_DYNAREC] Add la64 avx cvt ops, part 3. (#2869)phorcys2025-08-015-0/+237
| | | | | | | Double <=> Integer convert. Half Float <=> Integer convert. VCVT{DQ2PD, PD2DQ, TPD2DQ} VCVT{SI2SD, SD2SI, TSD2SI} VCVT{PH2PS, PS2PH}
* [INTERP] Try to improve aligned LOCK CMPXCHG8B opcodeptitSeb2025-08-017-1/+66
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* [LA64_DYNAREC] Add la64 avx cvt ops, part2. (#2866)phorcys2025-08-013-0/+158
| | | | | Integer <=> Float convert. VCVT{DQ2PS, PS2DQ, TPS2DQ} VCVT{SI2SS, SS2SI, TSS2SI}
* [RV64_DYNAREC] Fixed a typo (#2865)Yang Liu2025-07-312-7/+9
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* [LA64_DYNAREC] Add la64 avx cvt ops, part1. (#2859)phorcys2025-07-316-1/+157
| | | | | | Double <=> Float ops, VROUND ops. VCVT{PD2PS,PS2PD, SD2SS, SS2SD} Round{PD,PS,SD,SS}
* [LA64_DYNAREC] Add la64 avx cmp ops, part3. TEST ops. (#2857)phorcys2025-07-304-11/+203
| | | | VPTEST VTESTPD, VTESTPS