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* [ARM64_DYNAREC] Added Calling Convention as comment in emitter, for referenceptitSeb2024-07-051-0/+35
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* [ARM64_DYNAREC] Improved 0F C7 /6 opcodeptitSeb2024-07-041-2/+23
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* [DYNAREC] Fixed IMUL sign extension issue (#1639)Yang Liu2024-07-045-34/+26
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* [LA64_DYNAREC] Fixed F2 0F 70 PSHUFLW opcode (#1634)Yang Liu2024-07-041-1/+8
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* [RV64_DYNAREC] Added preliminary RVV infra and PXOR opcode for demonstration ↵Yang Liu2024-07-049-92/+416
| | | | | | | | | | | | | (#1632) * [RV64_DYNAREC] Added preliminary RVV infra and PXOR opcode for demonstration * keep sse_cache_s uint8_t as suggested * use xor to do the wrap * revert * better fallback
* [RV64_DYNAREC] modify DF default /4 opcode (#1633)LiZhuoheng2024-07-041-5/+14
| | | | | * [RV64_DYNAREC] modify DF default /4 opcode * [RV64_DYNAREC] added DF default /4 opcode
* [RV64_DYNAREC] Added DF default /4 opcode (#1631)LiZhuoheng2024-07-031-0/+27
| | | | | * [RV64_DYNAREC] Added DF default /4 opcode * replace tabs to spaces
* Add missing func declarations: `get_first_jump_addr` (#1627)Yip Coekjan2024-07-022-0/+2
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* [DYNAREC] Improved cache coherency and internal jump handling, ↵ptitSeb2024-07-025-4/+52
| | | | [ARM64_DYNAREC] Improved YMM register tracking
* [DYNAREC] Reset fpu scratch after Instruction epilogptitSeb2024-07-011-2/+1
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* [DYNAREC] Keep internal jmp table to the endptitSeb2024-07-011-3/+4
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* [ARM64_DYNAREC] Fixed some regression on internal jumpsptitSeb2024-07-012-2/+2
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* [ARM64_DYNAREC] Added 64/65 70-7F/EB opcodesptitSeb2024-06-301-0/+22
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* {ARM64_DYNAREC] Small optimisation on F3 0F BC/BD opcodesptitSeb2024-06-281-12/+20
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* [ARM64_DYNAREC] Fixed printer for DUP opcodeptitSeb2024-06-281-1/+1
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* [ARM64_DYNAREC] Added AVX.66.0F38 91/93 opcodesptitSeb2024-06-281-0/+74
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* [ARM64_DYNAREC] Fixed AVX.66.0F3A 06/46/21 opcodesptitSeb2024-06-281-40/+6
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* [RV64_DYNAREC] Added vector instructions emitter (#1621)Yang Liu2024-06-271-79/+533
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* [ARM64_DYNAREC] Improved commentptitSeb2024-06-261-1/+2
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* small fix for ROR and ROL (#1618)liuli2024-06-261-2/+2
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* [ARM64_DYNAREC] Small fixes to 0F C7 /6 opcodeptitSeb2024-06-251-3/+4
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* [RV64_DYNAREC] Fixed regression on D9 E5 FXAM opcode (#1616)Yang Liu2024-06-251-4/+9
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* [COSIM] Added range handling in BOX64_DYNAREC_TEST ([RCFILE] too)ptitSeb2024-06-241-1/+1
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* [ARM64_DYNAREC] Added 0F C7 /6 opcode, with hardware support if presentptitSeb2024-06-242-0/+21
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* [ARM64_DYNAREC] Fixed AVX.66.0F38 90/92 opcodesptitSeb2024-06-241-10/+12
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* [ARM64_DYNAREC] Minor fix on printer for SMOV/UMOVptitSeb2024-06-241-6/+4
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* [ARM64_DYNAREC] Reworked ymm_zero handling on internal jumpptitSeb2024-06-234-17/+25
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* [DYNAREC] Try to limit UpdateFlags on internal jumpsptitSeb2024-06-237-9/+19
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* [ARM64_DYNAREC] Some small optims to a few AVX opcodesptitSeb2024-06-233-6/+44
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* Small improvment to 0F BC/BD opcodes ([ARM64_DYNAREC] too)ptitSeb2024-06-231-4/+4
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* [ARM64_DYNAREC] Fixed printer for MOVI_64ptitSeb2024-06-231-2/+2
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* [ARM64_DYNAREC] Small optim on 0F BC/BD opcodesptitSeb2024-06-231-4/+8
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* [ARM64_DYNAREC] Fixed an issue with fpuCacheTransform (possible regression)ptitSeb2024-06-221-2/+2
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* Added 66 F2/F3 A4 opcode ({DYNAREC] too)ptitSeb2024-06-223-2/+91
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* [ARM64_DYNAREC] Small improvement to 0F 5D/5F opcodesptitSeb2024-06-221-10/+6
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* [ARM64_DYNAREC] Improved AVX.66.0F38 2E/2F to avoid segfault when mask is nullptitSeb2024-06-211-9/+59
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* [RV64_DYNAREC] Added unaligned support for F0 /5 LOCK SUB opcode (#1607)Yang Liu2024-06-201-1/+21
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* [ARM64_DYNAREC] Fixed AVX.F2.0F3A F0 opcodeptitSeb2024-06-191-0/+1
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* Update arm64_immenc.c (#1602)salt4312024-06-191-71/+73
| | | | | combine if (!bitmask || !~bitmask) to (bitmask == 0 || bitmask == ~0ULL) to reduce overhead. use bitwise operators instead of + operators.
* [RV64_DYNAREC] Fixed potential issue of jump_to_next (#1600)Yang Liu2024-06-182-3/+3
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* [ARM64_DYNAREC] Added a warning if allocating a scratch register after some YMMptitSeb2024-06-181-0/+2
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* [ARM64_DYNAREC] Fixed AVX.66.0F 6B opcodeptitSeb2024-06-181-2/+2
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* [ARM64_DYNAREC] Restaured a better way to handle ymm register, now that the ↵ptitSeb2024-06-183-24/+18
| | | | traking is improved
* [ARM64_DYNAREC] Fixed AVX.66.0F3A 19/39 opcodesptitSeb2024-06-181-3/+8
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* [ARM64_DYNAREC] Better tracking of used ymm (seems redundent with ymm0_sub)ptitSeb2024-06-181-13/+16
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* [RV64_DYNAREC] Improved 0F AE opcodes (#1596)Yang Liu2024-06-181-23/+23
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* [LA64_DYNAREC] Added more opcodes (#1597)Yang Liu2024-06-1811-0/+245
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* [RV64_DYNAREC] Fixed and refined F0 81,83 LOCK prefix opcodes (#1595)Yang Liu2024-06-181-15/+19
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* [ARM64_DYNAREC][COSIM] Do not test atomic operatin, they don't support ↵ptitSeb2024-06-171-0/+1
| | | | double execution very well by nature
* [LA64_DYNAREC] Added more opcodes (#1590)Yang Liu2024-06-176-3/+197
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