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* [ARM64_DYNAREC] Small optim on flag computation for 69 opcodeptitSeb2024-03-021-6/+54
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* [LA64_DYNAREC] Added more opcodes with CALL/RET optimization (#1310)Yang Liu2024-03-025-1/+159
| | | | | | | * [LA64_DYNAREC] Added FF /2 CALL Ed opcode * [LA64_DYNAREC] Added 81/83 /0 ADD opcode * [LA64_DYNAREC] Added C3 RET opcode
* [LA64_DYNAREC] Adopt to ARM64 way of CALL/RET optim since there is a ↵Yang Liu2024-03-022-7/+5
| | | | dedicated register (#1309)
* [LA64_DYNAREC] Added xSavedSP to emitter for later useptitSeb2024-03-021-0/+1
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* [LA64_DYNAREC] Added 70-7F Jcc opcodes, refine printer and some fixes too ↵Yang Liu2024-03-0212-124/+875
| | | | | | | | | | | | | | | | | | | | | | | | | (#1307) * [LA64_DYNAREC] Added 70-7F Jcc opcodes and some fixes too * [LA64_DYNAREC] Added more instructions to the printer and made the format prettier * Make LBT truely optional * Do not test LBT in CI * Format * Optimize * Fixed printer format * Fixed CLEAR_FLAGS macro * Fixed xMASK * Use $r22 ($sp) in the prolog/epilog for better semantics * Fixed la64_next
* Added 66 F8/F9 ([ARM64_DYNAREC] too)ptitSeb2024-03-011-0/+12
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* [LA64_DYNAREC] Added 1 more opcode and more fixes (#1305)Yang Liu2024-02-296-5/+87
| | | | | | | | | * Fixed printer name mapping * Fixed emit_sub32c * Remove a useless macro * Added 85 TEST opcode
* [LA64_DYNAREC] Added more opcodes and fixed more things (#1304)Yang Liu2024-02-295-19/+45
| | | | | | | | | | | * [LA64_DYNAREC] Fixed GETED macro * [LA64_DYNAREC] Added 81/83 /5 SUB opcode * Use xMASK when possible * Added 8B MOV opcode * Fix
* [LA64_DYNAREC] Added LBT support to all implemented emit functions and fixed ↵Yang Liu2024-02-291-24/+100
| | | | some typos (#1303)
* [LA64_DYNAREC] Added basic LBT support, setup xMASK (#1302)Yang Liu2024-02-294-13/+26
| | | | | * [LA64] Added basic LBT support, setup xMASK * [CI] Run tests without LBT
* [LA64_DYNAREC] Removed F_OF2 trick as it's unnecessary (#1300)Yang Liu2024-02-294-28/+6
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* [LA64_DYNAREC] Added some LBT instructions (#1299)Yang Liu2024-02-291-1/+174
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* [LONGAARCH_DYNAREC] Added 00...05 and 28...2D opcodes (#1297)Haichen Wu2024-02-2915-93/+1122
| | | | | * [LONGAARCH] More renamed arch to LA64 * [LONGAARCH_DYNAREC] Added 00...05 and 28...2D opcodes
* [LONGAARCH] Renamed arch to LA64, as LA464 is code name for 3a5000, so that ↵ptitSeb2024-02-2824-181/+181
| | | | way it's more generic (and sorry about that late minute change)
* LARCH64 dynarec (#1295)Haichen Wu2024-02-2820-0/+2307
| | | | | * LARCH64_DYNAREC dynarec * [LARCH64_DYNAREC] Change mapping for the registers
* [RV64_DYNAREC] Fixed RDTSC handling (#1291)Yang Liu2024-02-271-15/+45
| | | | | | | | | | | | | * [LIBWRAP] Fixed a typo in the clocksource wrapping * [RV64_DYNAREC] Added hardware timer support for RDTSC * [INTERP] Optmize RV64 ReadTSC using rdtime * [RV64_DYNAREC] Added 0F 01 F9 RDTSCP opcode * Fixed typo * Fixed another typo
* [ARM64_DYNAREC] Added FF /3 opcodeptitSeb2024-02-271-0/+41
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* [ARM64_DYNAREC] copied code for F0 87 to 87 opcode, as they should behavee ↵ptitSeb2024-02-271-5/+9
| | | | the same way
* [32BITS][ARM64_DYNAREC] Added 67 E0..E3 opcodesptitSeb2024-02-271-0/+60
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* [RV64_DYNAREC] Optimized XOR Ew, Gw when Ew == Gw (#1289)xctan2024-02-271-8/+62
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* [ARM64_DYNAREC] Added C8 opcode (for CP2077)ptitSeb2024-02-271-1/+25
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* [ARM64_DYNAREC] Added 66 F0 01 opcode (for CP2077)ptitSeb2024-02-271-0/+31
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* [ARM64_DYNAREC] Fixed a potential issue with F0 87 opcodeptitSeb2024-02-271-1/+1
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* [32BITS] Added 0E opcode ([ARM64_DYNAREC] too)ptitSeb2024-02-241-1/+10
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* Added 0F 01 F9 opcode ([ARM64_DYNAREC] tooptitSeb2024-02-241-0/+12
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* [ARM64_DYNAREC] Handling of EB FF hacky jumpptitSeb2024-02-241-24/+30
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* [RV64_DYNAREC] Added missing 0F 38 00 PSHUFB opcode for test23 (#1282)Yang Liu2024-02-231-0/+17
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* [RV64_DYNAREC] Added all missing 66 0F opcodes for test17 (#1281)Yang Liu2024-02-231-1/+91
| | | | | | | | | | | | | * Added 66 0F 38 14 PBLENDVPS opcode * Added 66 0F 3A 40 DPPS opcode * Added 66 0F 38 20 PMOVSXBW opcode * Added 66 0F 38 21 PMOVSXBD opcode * Added 66 0F 38 22 opcode * Added 66 0F 38 23/24 opcodes
* Better handling of Hardware counter for rdtsc emulation (ARM64 only for ↵ptitSeb2024-02-232-1/+7
| | | | now), more cpuid leafs, and introduce BOX64_RDTSC env.var. with a profile that use it
* Added 67 FF /2 opcode ([ARM64_DYNAREC] too)ptitSeb2024-02-221-0/+48
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* [RV64_DYNAREC] Added 2 more 66 0F opcodes for test17 (#1278)Yang Liu2024-02-222-18/+70
| | | | | * Added 66 0F 38 03 PHADDSW opcode * Added 66 0F 38 05 PHSUBW opcode
* [RV64_DYNAREC] Added more opcodes (#1277)Yang Liu2024-02-223-0/+82
| | | | | | | | | * Added 66 0F 38 25 PMOVSXDQ opcode * Added 0F 3A CC opcode * Added 67 F7 /4 MUL opcode * Added 67 C1 /5 SHR opcode
* [ARM64_DYNAREC] Added 0F E2 opcodeptitSeb2024-02-221-0/+14
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* [RV64_DYNAREC] Added more opcodes (#1276)Yang Liu2024-02-227-31/+68
| | | | | | | | | * Added 66 9C/9D PUSHF/POPF opcodes * Added 0F E2 PSRAD opcode * Fix * More readable
* [ARM64_DYNAREC] Added RCR 8bits with constant optimisation, and fixed RCL ↵ptitSeb2024-02-213-15/+59
| | | | 8bit with const
* [ARM64_DYNAREC] Optimized rcl 8bits with constantptitSeb2024-02-213-25/+55
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* [ARM64] Used Hardware counter for RDTSC emulation ([ARM64_DYNAREC] too)ptitSeb2024-02-212-4/+5
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* [DYNAREC_RV64] Minor OF flag fixes and optimizations for emit shift utils ↵Yang Liu2024-02-213-100/+118
| | | | | | | (#1275) * Minor OF flag fixes and optimizations for emit shift utils * original operand
* [ARM64_DYNAREC] Fixed some inf/nan detection for FXAM opcodeptitSeb2024-02-211-2/+1
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* [ARM64_DYNAREC] Adjusted some FLAGS productions of AAA/AAS/DAA/DAS ocpodesptitSeb2024-02-211-4/+4
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* [ARM64_DYNAREC] Fixed some case of ROL/ROR 8/16bits not computing CF flag ↵ptitSeb2024-02-203-24/+20
| | | | correctly
* [DYNAREC_RV64] Added more opcodes and some minor optimizations (#1272)Yang Liu2024-02-207-39/+126
| | | | | | | * Added DD /1 FISTTP i64 opcode * Some small optimizations * Added 0F AD SHRD opcode and some minor optimizations on the CF flag computation
* [DYNAREC] Adjusted the PUSH/POP x87 macro (and fix RV64 test infinite loop)ptitSeb2024-02-172-6/+3
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* [ARM64_DYNAREC] Added F0 31 opcodeptitSeb2024-02-171-0/+51
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* [ARM64_DYNAREC] Added unligned path for F0 01 and F0 39ptitSeb2024-02-171-1/+46
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* [RV64_DYNAREC] Fix buildptitSeb2024-02-171-3/+3
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* [DYNAREC] Try to fix some issue with x87 stack and skipped code being incoherentptitSeb2024-02-1712-102/+183
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* [ARM64_DYNAREC] Fixed D9 E4 opcodeptitSeb2024-02-171-2/+2
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* Better handling of 26/2E/36/3E prefix on F0 prefixed opcode ([ARM64_DYNAREC] ↵ptitSeb2024-02-171-0/+4
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* Added 67 C6 opcode ([ARM64_DYNAREC] too)ptitSeb2024-02-171-0/+28
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