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* [RV64_DYNAREC] Added MMX handling to `fpu_{push,pop}cache` for vector (#2858)Yang Liu2025-07-301-5/+28
* [LA64_DYNAREC] Add la64 avx int cmp ops. (#2856)phorcys2025-07-294-7/+146
* [RV64][LA64] Added partial FLUSHTO0 support (#2855)Yang Liu2025-07-293-7/+123
* [ARM+4_DYNAREC] Another fix for STMXCSR opcode when using SSE_FLUSHTO0ptitSeb2025-07-291-1/+1
* [ARM+4_DYNAREC] Fixed (V)[LD/ST]MXCSR opcodes when using SSE_FLUSHTO0ptitSeb2025-07-292-35/+35
* [LA64_DYNAREC] Add la64 avx float cmp ops. (#2854)phorcys2025-07-295-17/+132
* [LA64_DYNAREC] Add la64 avx float ops part 3. (#2845)phorcys2025-07-298-30/+408
* [DYNAREC] Fixed an issue introduced with 48ae536d95390b98add016866948e9152294...ptitSeb2025-07-262-23/+49
* [LA64_DYNAREC] Fixed some issue with ADD/SUB x64 eflags when using LBT extensionptitSeb2025-07-241-10/+10
* Some handling of case where signal numbers differs between native and x64 arc...ptitSeb2025-07-235-11/+12
* [RV64_DYNAREC][LA64_DYNAREC] Simplified defered flags handling and limited ca...Yang Liu2025-07-234-56/+39
* [LA64_DYNAREC] Add la64 avx float ops VDPP{S,D}, VH{ADD,SUB}{PS,PD} (#2842)phorcys2025-07-236-4/+191
* [LA64_DYNAREC] Add la64 avx float arith ops, part 1. (#2840)phorcys2025-07-225-0/+385
* [LA64_DYNAREC] Add la64 avx FMA insts. (#2838)phorcys2025-07-224-1/+473
* [LA64_DYNAREC] add la64 avx pack/unpack ops, part5. (#2837)phorcys2025-07-213-32/+340
* [DYNAREC] Consolidate access to native register in signal and register mappin...ptitSeb2025-07-214-266/+280
* [DYNACACHE]LA64] Enabled dynacache for LA64 (#2836)Yang Liu2025-07-215-32/+92
* [LA64_DYNAREC] add la64 avx pack/unpack ops, part4. (#2830)phorcys2025-07-218-16/+288
* [LA64_DYNAREC] Add la64 avx pack/unpack ops , part 3 blend ops. (#2824)phorcys2025-07-202-3/+228
* [DYNAREC] Change an error to warning, when entering FillBlock64 and current_h...ptitSeb2025-07-191-4/+3
* [LA64_DYNAREC] Add la64 avx pack/unpack ops , part 2. (#2823)phorcys2025-07-183-2/+74
* [LA64_DYNAREC] Add la64 avx pack/unpack ops , part 1. (#2818)phorcys2025-07-173-1/+88
* [ARM64_DYNAREC] Added 64/65 F3 0F 7F opcodeptitSeb2025-07-161-0/+21
* [ARM64_DYNAREC] Small optim on (V/F)COMI(SS/SD) opcodesptitSeb2025-07-169-28/+48
* [ARM64_DYNAREC] Fixed a residual issue with xmm unneeded handling when unload...ptitSeb2025-07-151-1/+1
* [LA64_DYNAREC] Add la64 avx arith ops, part2. (#2816)phorcys2025-07-154-0/+307
* [LA64_DYNAREC] Optimized PMADDUBSW opcodes (#2817)Yang Liu2025-07-152-25/+18
* [LA64_DYNAREC] Add la64 avx arith ops , part 1. (#2814)phorcys2025-07-143-6/+357
* [LA64_DYNAREC] Fix la64 VMASKMOVPS,VMOVHPD. (#2811)phorcys2025-07-143-8/+8
* Merge remote-tracking branch 'refs/remotes/origin/main'ptitSeb2025-07-148-64/+407
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| * [LA64_DYNAREC] Add la64 avx shift ops. (#2806)phorcys2025-07-143-1/+205
| * [LA64_DYNAREC] Optimized some SSE shift opcodes (#2813)Yang Liu2025-07-141-58/+38
| * [LA64_DYNAREC] Add la64 avx BMI2 shift ops. (#2807)phorcys2025-07-145-5/+164
* | Improved Volatile Metadata handlingptitSeb2025-07-142-2/+2
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* [ARM64_DYNAREC] Added 0F 00 /0 opcodeptitSeb2025-07-121-1/+21
* [LA64_DYNAREC] Add la64 avx shift ops with imm operand. (#2805)phorcys2025-07-112-0/+175
* [LA64_DYNAREC] Fix/Opt la64 avx movsx/movzx ops. (#2804)phorcys2025-07-111-126/+34
* [ARM64_DYNAREC] Simplified defered flags handling and limited case where Upda...ptitSeb2025-07-109-42/+15
* [RCFILE] Fixed profile per lib/dll that was using default instead of curent e...ptitSeb2025-07-094-0/+7
* [ARM64_DYNAREC] Removed fastpath for (V)MINPD/MAXPD as it's too inexactptitSeb2025-07-092-32/+14
* [ARM64_DYNAREC] Fined tuned UD value for BSR/BSFptitSeb2025-07-092-4/+6
* [ARM64_DYNAREC] Fixed rare sideeffect of 32bits cmpxchg opcodeptitSeb2025-07-092-2/+4
* [ARM64_DYNAREC] Better handling of shift 0 for rcl/rct 16bitsptitSeb2025-07-091-0/+2
* [LA64_DYNAREC] Fix la64 avx->sse same reg migration. (#2801)phorcys2025-07-091-1/+3
* [LA64_DYNAREC] Opt/fix la64 avx mov ops. (#2800)phorcys2025-07-093-15/+6
* [LA64_DYNAREC] Add la64 avx bitwise ops. (#2780)phorcys2025-07-097-33/+305
* [LA64_DYNAREC] Fix VEX.0f.17 VMOVHPS, one break missing. (#2798)phorcys2025-07-051-0/+1
* [ARM64_DYNAREC] Small cosmetic change in indirect_lookupptitSeb2025-07-031-2/+4
* [ARM64_DYNAREC] Added unused LRCPC emittersptitSeb2025-07-031-0/+10
* [DYNAREC] Fixed a potential issue where defered flags are not computed/reset ...ptitSeb2025-07-024-4/+5