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* [RV64_DYNAREC] Added MMX handling to `fpu_{push,pop}cache` for vector (#2858)Yang Liu2025-07-301-5/+28
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* [LA64_DYNAREC] Add la64 avx int cmp ops. (#2856)phorcys2025-07-294-7/+146
| | | | VCMP{EQ,GT}{B,W,D,Q} VCOMISS, VUCOMISS, VCOMISD, VUCOMISD
* [RV64][LA64] Added partial FLUSHTO0 support (#2855)Yang Liu2025-07-293-7/+123
| | | | | | | | | | | * [RV64][LA64] Removed obselete TODOs * more * more * more * more
* [ARM+4_DYNAREC] Another fix for STMXCSR opcode when using SSE_FLUSHTO0ptitSeb2025-07-291-1/+1
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* [ARM+4_DYNAREC] Fixed (V)[LD/ST]MXCSR opcodes when using SSE_FLUSHTO0ptitSeb2025-07-292-35/+35
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* [LA64_DYNAREC] Add la64 avx float cmp ops. (#2854)phorcys2025-07-295-17/+132
| | | VCMPPD,VCMPPS,VCMPSD,VCMPSS
* [LA64_DYNAREC] Add la64 avx float ops part 3. (#2845)phorcys2025-07-298-30/+408
| | | | | | | | | * add cpuext.frecipe for LoongArch V1.1 * Fix VFRSQRTE in sse op RSQRTPS/RSQRTSS * Fix VFRECIPE in sse op RCPPS/RCPSS * V{MAX,MIN}{PD,PS,SD,SS} * VRCPPS,VRCPSS * VRSQRTPS,VRSQRTSS * VSQRT{PD,PS,SD,SS}
* [DYNAREC] Fixed an issue introduced with ↵ptitSeb2025-07-262-23/+49
| | | | 48ae536d95390b98add016866948e91522943730 and properly address the underlying issue
* [LA64_DYNAREC] Fixed some issue with ADD/SUB x64 eflags when using LBT extensionptitSeb2025-07-241-10/+10
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* Some handling of case where signal numbers differs between native and x64 ↵ptitSeb2025-07-235-11/+12
| | | | archs (not complete, missing sigset conversions)
* [RV64_DYNAREC][LA64_DYNAREC] Simplified defered flags handling and limited ↵Yang Liu2025-07-234-56/+39
| | | | case where UpdateFlags is actualy called (#2844)
* [LA64_DYNAREC] Add la64 avx float ops VDPP{S,D}, VH{ADD,SUB}{PS,PD} (#2842)phorcys2025-07-236-4/+191
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* [LA64_DYNAREC] Add la64 avx float arith ops, part 1. (#2840)phorcys2025-07-225-0/+385
| | | | * V{ADD,SUB,MUL,DIV}{PD,PS,SD,SS} * VADDSUB{PD,PS}
* [LA64_DYNAREC] Add la64 avx FMA insts. (#2838)phorcys2025-07-224-1/+473
| | | | * VF{MADD,MSUB,NMADD,NMSUB}{132,213,231}{PD,PS,SD,SS} * VFM{ADDSUB,SUBADD}{132,213,231}{PD,PS}
* [LA64_DYNAREC] add la64 avx pack/unpack ops, part5. (#2837)phorcys2025-07-213-32/+340
| | | | | | INSERT/EXTRACT/BROADCAST/GATHER ops. VEXTRACTPS,VINSERTPS VBROADCAST{SD,SS}, VPBROADCAST{B,W,D,Q,I128} VPGATHER{DD,DQ,QD,QQ,DPD,DPS,QPD,QPS}
* [DYNAREC] Consolidate access to native register in signal and register ↵ptitSeb2025-07-214-266/+280
| | | | mapping acrross all 3 supported dynarec archs
* [DYNACACHE]LA64] Enabled dynacache for LA64 (#2836)Yang Liu2025-07-215-32/+92
| | | | | * [DYNACACHE]LA64] Enabled dynacache for LA64 * review
* [LA64_DYNAREC] add la64 avx pack/unpack ops, part4. (#2830)phorcys2025-07-218-16/+288
| | | | | | | | | Shuf/Permute ops. VSHUFPS, VSHUFPD VPSHUFD, VPSHUFQ, VPSHUFB, VPSHUFLW, VPSHUFHW VPERMQ, VPERMD VPERMPD, VPERMPS VPERMILPD, VPERMILPS VPERM2F128, VPERM2I128
* [LA64_DYNAREC] Add la64 avx pack/unpack ops , part 3 blend ops. (#2824)phorcys2025-07-202-3/+228
| | | | | | VBLENDPD, VBLENDPS VPBLENDW, VPBLENDD, VPBLENDVB VBLENDVPD, VBLENDVPS VPALIGNR
* [DYNAREC] Change an error to warning, when entering FillBlock64 and ↵ptitSeb2025-07-191-4/+3
| | | | current_helper is not cleaned up
* [LA64_DYNAREC] Add la64 avx pack/unpack ops , part 2. (#2823)phorcys2025-07-183-2/+74
| | | | VUNPCK{LPS,LPD,HPS,HPD} VPUNPCK{LBW,LWD,LDQ,LQDQ,HBW,HWD,HDQ,HQDQ}
* [LA64_DYNAREC] Add la64 avx pack/unpack ops , part 1. (#2818)phorcys2025-07-173-1/+88
| | | | | | VPACKSSWB VPACKSSDW VPACKUSWB VPACKUSDW
* [ARM64_DYNAREC] Added 64/65 F3 0F 7F opcodeptitSeb2025-07-161-0/+21
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* [ARM64_DYNAREC] Small optim on (V/F)COMI(SS/SD) opcodesptitSeb2025-07-169-28/+48
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* [ARM64_DYNAREC] Fixed a residual issue with xmm unneeded handling when ↵ptitSeb2025-07-151-1/+1
| | | | unloading xmm9-xmm15 registers
* [LA64_DYNAREC] Add la64 avx arith ops, part2. (#2816)phorcys2025-07-154-0/+307
| | | | | * VEX.66.0F VPMADDWD,VPSADBW * VEX.66.0F.38 VPH{ADD,SUB}{W,D,SW}, VPABS{B,W,D} VPMADDUBSW,VPMULHRSW, * VEX.66.0F.3A VMPSADBW
* [LA64_DYNAREC] Optimized PMADDUBSW opcodes (#2817)Yang Liu2025-07-152-25/+18
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* [LA64_DYNAREC] Add la64 avx arith ops , part 1. (#2814)phorcys2025-07-143-6/+357
| | | | | | | | Add 1:1 avx arith ops. * VP{ADD,SUB}{B,W,D,Q,SB,SW,USB,USW} * VPMUL{DQ,,HW,HUW,Lw,LD,LUDQ} * V{MAX,MIN}{UB,UW,UD,SB,SW,SD} * VAVG{B,W} * VSIGN{B,W,D}
* [LA64_DYNAREC] Fix la64 VMASKMOVPS,VMOVHPD. (#2811)phorcys2025-07-143-8/+8
| | | | * fix la64 VMASKMOVPS,VMOVHPD. * fix arm64 VMASKMOVPS,VMASKMOVPD op memo operand order.
* Merge remote-tracking branch 'refs/remotes/origin/main'ptitSeb2025-07-148-64/+407
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| * [LA64_DYNAREC] Add la64 avx shift ops. (#2806)phorcys2025-07-143-1/+205
| | | | | | | | * VEX.66.0f VPSRLW/VPSRLDVPSRLQ/VPSRAW/VPSRAD/VPSLLW/VPSLLD/VPSLLQ * VEX.66.0f.3a VPSRLVD/VPSRLVQ/VPSRAVDVPSLLVD/VPSLLVQ
| * [LA64_DYNAREC] Optimized some SSE shift opcodes (#2813)Yang Liu2025-07-141-58/+38
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| * [LA64_DYNAREC] Add la64 avx BMI2 shift ops. (#2807)phorcys2025-07-145-5/+164
| | | | | | | | | | * VEX.66.0f.38 SHLX * VEX.f2.0f.38 SHRX * VEX.f3.0f.38 SARX
* | Improved Volatile Metadata handlingptitSeb2025-07-142-2/+2
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* [ARM64_DYNAREC] Added 0F 00 /0 opcodeptitSeb2025-07-121-1/+21
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* [LA64_DYNAREC] Add la64 avx shift ops with imm operand. (#2805)phorcys2025-07-112-0/+175
| | | | | | VEX.128/256 66.0F shift imm ops: * 71 VPSRLW/VPSRAW/VPSLLW * 72 VPSRLD/VPSRAD/VPSLLD * 73 VPSRLQ/VPSLLQ/VPSRLDQ/VPSLLDQ
* [LA64_DYNAREC] Fix/Opt la64 avx movsx/movzx ops. (#2804)phorcys2025-07-111-126/+34
| | | | | | Use vext2xv to opt movsx/movzx. For VEX.128 bw,wd,dq ops, use vsllwil(latency 2) instead of vext2xv (latency 3) Old imp use xvsllwil is wrong, because xvsllwil operate on per 128bits channel. But MOVSX/MOVZX VEX.256 ops only read src operand from low 128bits.
* [ARM64_DYNAREC] Simplified defered flags handling and limited case where ↵ptitSeb2025-07-109-42/+15
| | | | UpdateFlags is actualy called (could be simplified more) (TODO on RV64 and LA64)
* [RCFILE] Fixed profile per lib/dll that was using default instead of curent ↵ptitSeb2025-07-094-0/+7
| | | | env for non defined values
* [ARM64_DYNAREC] Removed fastpath for (V)MINPD/MAXPD as it's too inexactptitSeb2025-07-092-32/+14
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* [ARM64_DYNAREC] Fined tuned UD value for BSR/BSFptitSeb2025-07-092-4/+6
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* [ARM64_DYNAREC] Fixed rare sideeffect of 32bits cmpxchg opcodeptitSeb2025-07-092-2/+4
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* [ARM64_DYNAREC] Better handling of shift 0 for rcl/rct 16bitsptitSeb2025-07-091-0/+2
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* [LA64_DYNAREC] Fix la64 avx->sse same reg migration. (#2801)phorcys2025-07-091-1/+3
| | | | | In current code, if an avx reg writed reg is used by following sse inst. A VLD would emitted by sse_get_reg, causing prev avx inst writed content lose. Skip sse_get_reg's VLD emit, when reg content is already load/changed in prev avx inst.
* [LA64_DYNAREC] Opt/fix la64 avx mov ops. (#2800)phorcys2025-07-093-15/+6
| | | | | | * opt VEX.66.0F.D6 VMOVD * opt VEX.F2.0F.10 VMOSD * opt VEX.F3.0F.10 VMOVSS * opt/fix VEX.F3.0F.7E VMOVD
* [LA64_DYNAREC] Add la64 avx bitwise ops. (#2780)phorcys2025-07-097-33/+305
| | | | | | | * avx VEX.66.0F 54/55/56/57 VANDPD/VANDNPD/VORPD/VXORPD * avx VEX.0F 54/55/56/57 VANDPS/VANDNPS/VORPS/VXORPS * avx VEX.66.0F DB/DF/EB/EF VPAND/VPANDN/VPOR/VPXOR * bmi1 VEX.0F38 F2 ANDN * bmi2 VEX.F2.0F3A F0 RORX
* [LA64_DYNAREC] Fix VEX.0f.17 VMOVHPS, one break missing. (#2798)phorcys2025-07-051-0/+1
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* [ARM64_DYNAREC] Small cosmetic change in indirect_lookupptitSeb2025-07-031-2/+4
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* [ARM64_DYNAREC] Added unused LRCPC emittersptitSeb2025-07-031-0/+10
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* [DYNAREC] Fixed a potential issue where defered flags are not computed/reset ↵ptitSeb2025-07-024-4/+5
| | | | on internal jump