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* [ARM64_DYNAREC] Improved shld16 opcodeptitSeb2024-01-271-8/+6
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* [ARM64_DYNAREC] Fixed 66 8C opcode and improved many 66 prefix opcode on 32BITSptitSeb2024-01-272-29/+30
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* [ARM64_DYNAREC] Removed unused codeptitSeb2024-01-273-36/+0
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* [ARM64_DYNAREC] Fixed/Improved D9 E5 opcode and add hack for ↵ptitSeb2024-01-271-6/+85
| | | | FLD1/FLD1/FPATAN sequence
* [ARM64_DYNAREC] Fixed previous commitptitSeb2024-01-261-3/+3
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* Reworked 0F 01 opcode ([ARM64_DYNAREC] too)ptitSeb2024-01-261-9/+30
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* Added 66 8F opcode ([ARM64_DYNAREC] too)ptitSeb2024-01-261-19/+30
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* [32BITS] Added 16/17 ocodes ([ARM64_DYNAREC] too)ptitSeb2024-01-261-1/+19
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* [ARM64_DYNAREC] Fixed 67 66 prefixed REX readingptitSeb2024-01-241-0/+1
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* Added a new option BOX64_MMAP32 to use 32bits mapping on external MMAP (help ↵ptitSeb2024-01-231-0/+3
| | | | Snapdragon device running Vulkan with Wine/Wow64, active by default on SD845/SD888/SD8G2 profiles)
* [DYNAREC] use an rbtree for dynablock size and max_db_size updateptitSeb2024-01-231-4/+32
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* [DYNAREC_RV64] Enable basic simple wrapper optimization (#1215)Yang Liu2024-01-232-23/+19
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* [DYNAREC] Fixed a warningptitSeb2024-01-181-1/+1
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* [DYNAREC] Test when changing page on building a dynablock if it's safeptitSeb2024-01-181-0/+18
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* [ARM64_DYNAREC] Fixed some special case for shrd/shld opcodesptitSeb2024-01-162-32/+14
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* [RV64_DYNAREC] Fixed 66 87 XCHG opcode (#1198)xctan2024-01-131-2/+4
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* [RV64_DYNAREC] Fixed 66 0F B6 MOVZX opcode (#1196)xctan2024-01-111-0/+1
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* [DYNAREC_RV64] Added more opcodes and fixed X87_PUSH/POP macros (#1194)Yang Liu2024-01-095-16/+92
| | | | | | | | | | | * [DYNAREC_RV64] Added DB F0..F7 FCOMI opcodes * [DYNAREC_RV64] Added more DA opcodes * Try to fix X87_PUSH_OR_FAIL * [DYNAREC_RV64] Added D7 XLAT opcode * Fix X87_PUSH_OR_FAIL for aarch64 too
* [DYNAREC_RV64] Fixed a wrong Zba optimization (#1193)Yang Liu2024-01-091-10/+20
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* [ARM64_DYNAREC] Fixed 66 0F 3A 17 opcode (should help UE games)ptitSeb2024-01-081-1/+1
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* [INTERPRETER] Added 67 66 8D opcode ([ARM64_DYNAREC] too)ptitSeb2024-01-061-0/+15
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* [INTERPRETER] Improved 0F 01 opcode ([ARM64_DYNAREC] too)ptitSeb2024-01-061-10/+24
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* [DYNAREC_RV64] Added CALL/RET optimization (#1183)Yang Liu2024-01-055-36/+63
| | | | | | | | | | | * [DYNAREC_RV64] Added CALL/RET optimization * More hacks on the call/ret optimization * Small fixes, but still not working * More fixes * More fixes
* [ARM64_DYNAREC] A few more FRINTTS extension useptitSeb2024-01-051-32/+44
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* [ARM64_DYNAREC] More FRINTTS useptitSeb2024-01-053-33/+61
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* [ARM64_DYNAREC] Attempt to use FRINTTS extensionptitSeb2024-01-051-57/+54
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* [ARM64_DYNAREC] Simplified a bit CALLRET fallback handling on stack unsyncptitSeb2024-01-052-10/+3
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* [ARM64_DYNAREC] Fixed CALLRET optim when unsync occur, should help stabilityptitSeb2024-01-041-2/+2
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* [ARM64_DYNAREC] Some more warning fixesptitSeb2023-12-312-4/+5
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* Fixed some (nasty sometimes) warningptitSeb2023-12-312-4/+4
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* [MEMORY] Switched from a sparse array to a red-black tree (#1180)rajdakin2023-12-312-25/+0
| | | | | * [MEMORY] Switched from a sparse array to an RB tree * [RBTREE] Fixed the Android build
* [DYNAREC_RV64] Fixed a nasty bug in GETEX, but left optim opportunity for ↵Yang Liu2023-12-281-2/+4
| | | | later (#1178)
* [DYNAREC_RV64] Added more opcodes for VMP-protected GI (#1168)xctan2023-12-264-37/+194
| | | | | | | | | | | | | | | | | | | | | * [DYNAREC_RV64] Added 66 0F B3 BTR opcode * [DYNAREC_RV64] Added 66 0F BA /7 BTC opcode * [DYNAREC_RV64] Added 66 {D1,D3} /{2,3} RCL/RCR opcodes * [DYNAREC_RV64] Added 66 0F BA /{5,6} BTS/BTR opcodes * [DYNAREC_RV64] Added 0F C1 XADD opcode * [DYNAREC_RV64] Added 0F C0 XADD opcode * [DYNAREC_RV64] Added D3 /2 RCL opcode * [DYNAREC_RV64] Removed redundant declaration of wb2 in 0F * [DYNAREC_RV64] Enable 66 0F BD BSR again * [DYNAREC_RV64] Added 66 1D SBB opcode
* [DYNAREC_RV64] Added more opcodes for VMP-protected GI (#1164)xctan2023-12-257-6/+524
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * [DYNAREC_RV64] Added 66 0F C8-CF BSWAP opcode * [DYNAREC_RV64] Added 66 0F BB BTC opcode * [DYNAREC_RV64] Added D2 /3 RCR opcode * [DYNAREC_RV64] Added 66 0F BA /4 BT opcode * [DYNAREC_RV64] Added 66 D3 /1 ROR opcode * [DYNAREC_RV64] Added D2 /2 RCL opcode * [DYNAREC_RV64] Added 66 D3 /0 ROL opcode * [DYNAREC_RV64] Added 66 0F BC BSF opcode * [DYNAREC_RV64] Added 66 0F A4 SHLD opcode * [DYNAREC_RV64] Added 66 0F AB BTS opcode * [DYNAREC_RV64] Added 36 SS prefix * [DYNAREC_RV64] Added D3 /3 RCR opcode * [DYNAREC_RV64] Added C1 /3 RCR opcode * [DYNAREC_RV64] Added 66 0F AC SHRD opcode * [DYNAREC_RV64] Fixed emit_shrd16c, emit_shld16c declaration * [DYNAREC_RV64] Added C1 /2 RCL opcode * [DYNAREC_RV64] Added 66 0F BD BSR opcode * [DYNAREC_RV64] Added 66 0F A3 BT opcode * [DYNAREC_RV64] Added 66 0F C1 XADD opcode * [DYNAREC_RV64] Added 0F A5 SHLD opcode * [DYNAREC_RV64] Added C0 /2 RCL opcode * [DYNAREC_RV64] Added C0 /3 RCR opcode * [DYNAREC_RV64] Added 66 99 CWD opcode * [DYNAREC_RV64] Fixed 66 99 CWD opcode * [DYNAREC_RV64] Revert 66 0F BD BSR opcode VMP anti-debugger message will break with this opcode
* [DYNAREC_RV64] Added more opcodes for ets2 (#1162)Yang Liu2023-12-245-1/+112
| | | | | | | * [DYNAREC_RV64] Added F2 0F 7C HADDPS opcode * [DYNAREC_RV64] Added 0F 38 C8..CD opcodes * [DYNAREC_RV64] Added DF C0..C7 FFREEP opcodes
* [DYNAREC_RV64] Ported INT 3/29 from arm (#1161)xctan2023-12-241-6/+13
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* [DYNAREC_RV64] Fixed shift masks for GI (#1160)xctan2023-12-242-7/+9
| | | | | | | * [DYNAREC_RV64] Fixed SHLD for GI * [DYNAREC_RV64] Fixed SHRD for GI * [DYNAREC_RV64] Fixed shamt mask of 16-bit shifts
* [DYNAREC_RV64] Added more opcodes for ets2 (#1158)Yang Liu2023-12-232-9/+68
| | | | | | | | | * [DYNAREC_RV64] Added F3 0F 52 RSQRTSS opcode * [DYNAREC_RV64] Added F0 81 /6 LOCK XOR opcode (aligned only) * [DYNAREC_RV64] Added F3 0F 16 MOVSHDUP opcode * Format
* [DYNAREC_RV64] Fixed some bugs in the dynarec for ETS2 (#1155)Yang Liu2023-12-222-4/+7
| | | | | * [DYNAREC_RV64] Fixed BSWAP * [DYNAREC_RV64] Fixed 0F C2 CMPPS opcode
* [DYNAREC_RV64] Added more opcodes and fixes (#1154)Yang Liu2023-12-225-4/+60
| | | | | | | | | | | * [DYNAREC_RV64] Added 66 0F 38 28 PMULDQ opcode * [DYNAREC_RV64] Added DD /6 FSAVE opcode * [DYNAREC_RV64] Added 66 8C MOV opcode * [DYNAREC_RV64] Fixed DF /1 /2 opcodes * [DYNAREC_RV64] Added DB /1 FISTTP opcode
* [ARM64_DYNAREC] Added 64/65 23 opcodeptitSeb2023-12-221-0/+10
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* [ARM64_DYNAREC] Partial rollback of previous commit, it was not goodptitSeb2023-12-222-22/+23
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* [ARM64_DYNAREC] Small optim on CF flag computation for 8/16bits add/sub ↵ptitSeb2023-12-222-29/+25
| | | | operations
* Added/Fix some 16bits PUSH POP opcode ([ARM64_DYNAREC] too) (for ↵ptitSeb2023-12-211-55/+27
| | | | DaveTheDiver, but not enough for it to run yet)
* Removed old commented codeptitSeb2023-12-201-9/+0
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* [DYNAREC_RV64] Added FILD/FISTP i64 optimization (#1145)Yang Liu2023-12-186-107/+244
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* [DYNAREC_RV64] Fixed some bugs in x87 infra (#1143)Yang Liu2023-12-181-10/+16
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* [ARM64_DYNAREC] fix emit_shld16(c) (#1141)liuli2023-12-151-4/+10
| | | | | | | | | | | | | | 0x1a46b618: 66 44 0F A4 F8 5B SHLD Ew, Gw, Ib 0x7f53749bdc: 7 emitted opcodes, inst=2, barrier=0 state=3/1(1), set=3F/1, use=0, need=0/1, sm=0/0, pred=1, last_ip=0x1a46b610 53003d41 UXTH w1, wEAX 53003f22 UXTH w2, wR15 2a024021 ORR w1, w1, w2, LSL 16 fff57c24 247CF5FF ??? 3300009a BFXIL wFlags, w4, 0, 1 13811421 ROR w1, w1, 5 b3403c2a BFXIL xRAX, x1, 0, 16 ??? rases SIGILL... Change-Id: I8f4afe3a814f8ee012bfc467261b32a9585d354b
* [DYNAREC] Fixed a bug with latest dynarec changesptitSeb2023-12-131-1/+1
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* [DYNAREC] Made callret default, improved callret efficiency, and dynarec ↵ptitSeb2023-12-139-36/+88
| | | | speed on larger blocks