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* [LA64_DYNAREC] Add adc8, adc8c, adc16 and testadc (#2069)Leslie Zhai2024-11-256-0/+293
| | | | | | | | | * [LA64_DYNAREC] Add adc8, adc8c, adc16 and testadc * [LA64_DYNAREC] Add missing testcase * [LA64_DYNAREC] Change ANDI+OR to BSTRINS_D for ADC AL, Ib and removed testadc * [LA64_DYNAREC] clang-format
* [ARM64_DYNAREC] Use YIELD instead of WFE (#2066)Yang Liu2024-11-243-1/+15
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* [RV64_DYNAREC] Added, fixed, and optimized opcodes (#2059)xctan2024-11-245-119/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Added 66 0F 38 37 PCMPGTQ opcode * [RV64_DYNAREC] Added 66 0F 17 MOVHPD opcode * [RV64_DYNAREC] Added 66 0F 38 15 PBLENDVPD opcode * [RV64_DYNAREC] Optimized vector SSE packed compare * [RV64_DYNAREC] Optimized vector MMX MOVD Gm, Ed * [RV64_DYNAREC] Optimized vector SSE PMADDWD opcode * [RV64_DYNAREC] Added vector PCMPGTQ opcode * [RV64_DYNAREC] Added vector 66 0F 17 MOVHPD opcode * [RV64_DYNAREC] Optimized vector 66 0F 16 MOVHPD opcode * [RV64_DYNAREC] Added vector PBLENDVPD opcode * [RV64_DYNAREC] Optimized vector PMADDUBSW opcode * [RV64_DYNAREC] Optimized vector SSE logical shifts with Ex * [RV64_DYNAREC] Optimized vector SSE unpack * [RV64_DYNAREC] Added F0 F6 /2 LOCK NOT opcode * [RV64_DYNAREC] Fixed vector packed logical shift
* [ARM64_DYNAREC] Fix a regression, as 90 opcode is not always NOP depending ↵ptitSeb2024-11-241-12/+14
| | | | on REX (should help #2064)
* [ARM64_DYNAREC] Generate corresponding hint instruction for PAUSE (#2063)Yang Liu2024-11-242-9/+13
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* [RV64_DYNAREC] Minor optimizations on CMPXCHG (#2062)Yang Liu2024-11-241-9/+3
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* [ARM64_DYNAREC] Small optim for emit_shld32c CF flag computationptitSeb2024-11-231-2/+1
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* [DYNAREC] Better detection of wait slotptitSeb2024-11-231-0/+15
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* Small fix for XSAVE/XRSTOR opcodes ([DYNAREC] too)ptitSeb2024-11-213-6/+6
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* [LA64_DYNAREC] Added more opcodes for JDK (#2055)Yang Liu2024-11-215-1/+272
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* [DYNAREC] Reuse strongmem infra for all backends (#2052)Yang Liu2024-11-21105-636/+302
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* [ARM64_DYNAREC] More optimizations on strongmem emulation (#2051)Yang Liu2024-11-202-42/+43
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* [ARM64_DYNAREC] Added weakbarrier=2 to disable last write barriers (#2049)Yang Liu2024-11-191-15/+15
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* [ARM64_DYNAREC] Re-enable weakbarrier for dmb.ishst (#2048)Yang Liu2024-11-191-4/+13
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* [DYNAREC] Reworked strong memory emulation (#2043)Yang Liu2024-11-1916-200/+571
| | | | | | | | | | | * [ARM64_DYNAREC] Reworked strong memory emulation * Simplify * [RV64,LA64_DYNAREC] Reworked strong memory emulation * forgot this * more tweaks
* Improved Signal handling ([ARM4_DYNAREC] too)ptitSeb2024-11-182-3/+8
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* [ARM64_DYNAREC] Only propagate native flags if at least 1 opcode consume themptitSeb2024-11-171-7/+14
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* [ARM64_DYNAREC] Cancel native flags when an opcode use native flags not ↵ptitSeb2024-11-171-6/+9
| | | | fully covered by the generated ones
* [ARM64_DYNAREC] Fixed potential issues with 0F A3/AB/B3/BB opcodesptitSeb2024-11-162-8/+13
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* [ARM64_DYNAREC] Small optim in emit_sar8c helperptitSeb2024-11-161-2/+1
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* [ARM64_DYNAREC] Various fixes and improvments to a few random opcodesptitSeb2024-11-157-68/+141
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* [DYNAREC] Zero'd upper 32bits of regs when switching to 32bits from 64bitsptitSeb2024-11-151-5/+18
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* [ARM64_DYNAREC] A few fixes to 8/16bits logic/math opcodesptitSeb2024-11-153-16/+16
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* [INTERPRETER] Some cleanup on base logic/math/shift operationsptitSeb2024-11-151-6/+0
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* [ARM64_DYNAREC] Try to not call UpdateFlags when switching to a DFNONE state ↵ptitSeb2024-11-1510-3/+39
| | | | but dfnone is not needed
* [ARM64_DYNAREC] Very small change on on emit_rol32c helperptitSeb2024-11-151-1/+1
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* [RV64_DYNAREC] Added more MMX opcodes for vector (#2037)xctan2024-11-152-0/+119
| | | | | | | | | | | | | * [RV64_DYNAREC] Added 0F 74-76 PCMPEQB/W/D opcodes * [RV64_DYNAREC] Added 0F 64-66 PCMPGTB/W/D opcodes * [RV64_DYNAREC] Added 0F E1-E2 PSRAW/D opcodes * [RV64_DYNAREC] Added 0F 6E MOVD opcode * [RV64_DYNAREC] Added 0F 73 /2 PSRLQ opcode * [RV64_DYNAREC] Added 0F 73 /6 PSLLQ opcode
* [ARM64_DYNAREC] Reworked 8/16/32/64bits TEST opcodesptitSeb2024-11-148-38/+236
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* [RV64_DYNAREC] Added more MMX opcodes for vector (#2035)xctan2024-11-141-0/+101
| | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Added 0F 68 PUNPCKHBW opcode * [RV64_DYNAREC] Added 0F 69 PUNPCKHWD opcode * [RV64_DYNAREC] Added 0F 6A PUNPCKHDQ opcode * [RV64_DYNAREC] Updated 0F 68-69 PUNPCKHBW/WD opcodes * [RV64_DYNAREC] Added 0F 60 PUNPCKLBW opcode * [RV64_DYNAREC] Added 0F 61 PUNPCKLWD opcode * [RV64_DYNAREC] Added 0F 62 PUNPCKLDQ opcode * [RV64_DYNAREC] Simplified MMX PUNPCK{L,H}{BW,WD,DQ}
* [DYNAREC] Added a experimental BOX64_DYNAREC_WEAKBARRIER option (#2033)Yang Liu2024-11-142-1/+15
| | | | | * [DYNAREC] Added a experimental BOX64_DYNAREC_WEAKBARRIER option * Added it to the RCFILE
* [ARM64_DYNAREC] Refactor 8/16/32/64bits CMP and REP CMPS/SCAS opcodesptitSeb2024-11-144-51/+115
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* [ARM64_DYNAREC] Some refactor on 8/16/32/64bits SHL/SHR/SAR opcodesptitSeb2024-11-143-79/+67
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* [ARM64_DYNAREC] Minor change on 16bits neg opcodeptitSeb2024-11-141-2/+0
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* [ARM64_DYNAREC] Some rework on 8/16/32/64 INC/DEC opcodesptitSeb2024-11-147-81/+36
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* [ARM64_DYNAREC] Small optim for 8/16/32/64bits adc/sbb opcodesptitSeb2024-11-131-32/+22
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* [ARM64_DYNAREC] Various small fixes for some 16bits math/logic opcodesptitSeb2024-11-136-36/+35
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* [RV64_DYNAREC] Added more MMX opcodes for vector (#2027)xctan2024-11-132-1/+79
| | | | | | | | | | | | | | | * [RV64_DYNAREC] Added 0F D5 PMULLW opcode * [RV64_DYNAREC] Added 0F E5 PMULHW opcode * [RV64_DYNAREC] Added 0F F5 PMADDWD opcode * [RV64_DYNAREC] Added 0F 6B PACKSSDW opcode * [RV64_DYNAREC] Added 0F 63 PACKSSWB opcode * [RV64_DYNAREC] Added 0F 67 PACKUSWB opcode * [RV64_DYNAREC] Removed useless vsetvli in MMX PACKUSWB/SSWB/SSDW
* [ARM64_DYNAREC] Reworked 8/16/32/64bits XOR opcodesptitSeb2024-11-136-84/+63
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* [ARM64_DYNAREC] Fixed previous commitptitSeb2024-11-133-46/+47
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* [ARM64_DYNAREC] Reworked 8/16/32/64 OR opcodesptitSeb2024-11-136-76/+62
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* [ARM64_DYNAREC] Reworked 8/16/32/64bits AND opcodesptitSeb2024-11-136-98/+94
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* [ARM64_DYNAREC] Small change in sbb32 helperptitSeb2024-11-131-1/+1
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* [ARM64_DYNAREC] Improved div/idiv opcode flags (non)handlingptitSeb2024-11-134-12/+60
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* [RV64_DYNAREC] Prefer AMO* instructions over LR/SC when possible (#2028)Yang Liu2024-11-134-123/+87
| | | | | * [RV64_DYNAREC] Prefer AMO* instructions over LR/SC when possible * fixes
* [ARM64_DYNAREC] Improved 32/64bits imul/mul opcodes flags handlingptitSeb2024-11-134-100/+184
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* [RV64_DYNAREC] Added more MMX opcodes for vector (#2026)xctan2024-11-131-0/+131
| | | | | | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Added 0F F8-FB PSUBB/W/D/Q opcodes * [RV64_DYNAREC] Added 0F E8 PSUBSB opcode * [RV64_DYNAREC] Added 0F D8-D9 PSUBUSB/W opcodes * [RV64_DYNAREC] Added 0F F1-F3 PSLLW/D/Q opcodes * [RV64_DYNAREC] Added 0F E9 PSUBSW opcode * [RV64_DYNAREC] Added 0F EB POR opcode * [RV64_DYNAREC] Added 0F DB PAND opcode * [RV64_DYNAREC] Added 0F DF PANDN opcode * [RV64_DYNAREC] Added 0F EF PXOR opcode * [RV64_DYNAREC] Optimized rvv MMX PSLLW/D/Q
* [RV64_DYNAREC] Added more MMX opcodes for vector (#2024)xctan2024-11-134-9/+103
| | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Added 0F D1-D3 PSRLW/PSRLD/PSRLQ opcode * [RV64_DYNAREC] Added 0F EC PADDSB opcode * [RV64_DYNAREC] Added 0F DC-DD PADDUSB/PADDUSW opcode * [RV64_DYNAREC] Added 0F FC-FE PADDB/PADDW/PADDD opcodes * [RV64_DYNAREC] Added 0F ED PADDSW opcode * [RV64_DYNAREC] Added 0F 7F MOVQ opcode * [RV64_DYNAREC] Fixed some typos * [RV64_DYNAREC] Optimized RVV MMX PSRLW/D/Q to a mask-less version
* [RV64_DYNAREC] Made eflags emulation branchless with xtheadcondmov (#2019)Yang Liu2024-11-1112-446/+295
| | | | | * [RV64_DYNAREC] Made eflags emulation branchless with xtheadcondmov * more
* [RV64_DYNAREC] Added more MMX opcodes for vector (#2017)Yang Liu2024-11-113-4/+43
| | | | | * [RV64_DYNAREC] Added more MMX opcodes for vector * fixed
* [ARM64_DYNAREC] A small optim for a specific case of 0F C6 opcodeptitSeb2024-11-091-0/+2
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