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* [RV64_DYNAREC] Added a fast path for some 16bit opcodes (#1765)Yang Liu2024-08-272-58/+73
* [ARM64_DYNAREC] Small refactor around get_segdata usageptitSeb2024-08-272-11/+15
* [RV64_DYNAREC] Added a fast path for some 8bit opcodes (#1763)Yang Liu2024-08-273-2/+75
* [ARM64_DYNAREC] Mark new upper YMM part as new, so the can be unwind too (for...ptitSeb2024-08-271-1/+2
* Added preliminary Box32 support (#1760)ptitSeb2024-08-266-37/+151
* [RV64_DYNAREC] Fix some typos in docs and dynarec/rv64 (#1758)WANG Guidong2024-08-269-24/+24
* [EMU] [ARM64_DYNAREC] Fix Some Warnings on Clang Compilers (#1757)KreitinnSoftware2024-08-261-1/+1
* [RV64_DYNAREC] Fixed more issues in the vector infrastructure (#1755)Yang Liu2024-08-258-66/+85
* More fixesYang Liu2024-08-251-2/+2
* Try to fix SSE type transformationYang Liu2024-08-243-29/+61
* [RV64,LA64_DYNAREC] Remove useless #if directivesYang Liu2024-08-202-11/+1
* Merge branch 'box32' into mainptitSeb2024-08-181-1/+1
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| * warn only onceYang Liu2024-08-181-1/+3
| * Slightly improved LOCK CMPXCHG16B opcodeYang Liu2024-08-181-4/+6
| * [RV64_DYNAREC] Added a warning on LOCK CMPXCHG16B opcodeYang Liu2024-08-181-0/+1
| * [BOX32] prepare elfheader_t structure for 32bits elfsptitSeb2024-08-171-1/+1
| * [RV64_DYNAREC] Added more opcodes (#1740)Yang Liu2024-08-164-47/+145
| * [LA64_DYNAREC] Port recent RV64 fixes (#1739)Yang Liu2024-08-165-43/+55
| * [RV64_DYNAREC] Added 66 0F 3A 63 PCMPISTRI opcode (#1735)Yang Liu2024-08-162-10/+39
| * [RV64,LA64_DYNAREC] Small change when handling long CC INT 3 opcode (#1736)Yang Liu2024-08-162-2/+6
* | [RV64_DYNAREC] Set the log level to Info for the LOCK CMPXCHG16B warning, to ...ptitSeb2024-08-181-1/+1
* | warn only onceYang Liu2024-08-171-1/+3
* | Slightly improved LOCK CMPXCHG16B opcodeYang Liu2024-08-171-4/+6
* | [RV64_DYNAREC] Added a warning on LOCK CMPXCHG16B opcodeYang Liu2024-08-171-0/+1
* | [RV64_DYNAREC] Added more opcodes (#1740)Yang Liu2024-08-164-47/+145
* | [LA64_DYNAREC] Port recent RV64 fixes (#1739)Yang Liu2024-08-165-43/+55
* | [RV64_DYNAREC] Added 66 0F 3A 63 PCMPISTRI opcode (#1735)Yang Liu2024-08-162-10/+39
* | [RV64,LA64_DYNAREC] Small change when handling long CC INT 3 opcode (#1736)Yang Liu2024-08-152-2/+6
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* [ARM64_DYNAREC] Small change when handling lone CC INT 3 opcodeptitSeb2024-08-151-1/+3
* [ARM64_DYNAREC] Added AVX.66.0F38 A6 opcodeptitSeb2024-08-151-3/+24
* [ARM64_DYNAREC] Added 67 90..97 opcodesptitSeb2024-08-151-0/+19
* [RV64_DYNAREC] Fixed extcacheUnwind regression (#1734)Yang Liu2024-08-151-8/+6
* [RV64_DYNAREC] Fixed 0F BA /5 BTS opcode (#1733)Yang Liu2024-08-121-2/+1
* [RV64_DYNAREC] More fixes (#1732)xctan2024-08-122-4/+4
* [ARM64_DYNAREC] Some small improvments to ROR/ROL/RCR/RCL opcodesptitSeb2024-08-115-110/+36
* [RV64_DYNAREC] Fixed flags for shrd/shld with constant 0 shift (#1730)Yang Liu2024-08-101-13/+23
* [RV64_DYNAREC] Fixed ROL/ROR RCX, CL (#1729)xctan2024-08-102-22/+14
* Added 67.AVX.0F.66 D6 opcode ([ARM64_DYNAREC] too)ptitSeb2024-08-101-0/+21
* Added 64bits 67 F3 0F 7F opcode ([ARM64_DYNAREC] too)ptitSeb2024-08-101-0/+13
* [ARM64_DYNAREC] Fixed flags for surd/shld with constant 0 shiftptitSeb2024-08-101-12/+22
* [ARM64_DYNAREC] Fixed pending flags for large 8 & 16 bit const shiftsptitSeb2024-08-101-0/+6
* [RV64_DYNAREC] Fixed pending flags for large 8 & 16 bit const shifts (#1728)xctan2024-08-101-0/+6
* [RV64_DYNAREC] Fixed more register conflicts (#1726)Yang Liu2024-08-093-8/+8
* [RV64_DYNAREC] Fixed OF generation in emit_sar16c (#1724)xctan2024-08-091-10/+4
* [ARM64_DYNAREC] Added AVX.66.0F38 9A opcodeptitSeb2024-08-091-2/+13
* [RV64_DYNAREC] Fixed fpu_flags handling and enabled cosim in CI (#1722)Yang Liu2024-08-091-0/+3
* [RV64_DYNAREC] Fixed misused BNE_NEXT in emit_ro{l,r}32 (#1723)xctan2024-08-091-4/+6
* [RV64_DYNAREC] Fixed FNSTSW opcode (#1721)Yang Liu2024-08-092-0/+5
* [DYNAREC_RV64] Removed TODOs on GETEX and GETEM macros (#1720)Yang Liu2024-08-096-306/+303
* [RV64_DYNAREC] Fixed register conflict in the GETSEB marco (#1719)xctan2024-08-091-1/+1