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* Added 67.AVX.0F.66 D6 opcode ([ARM64_DYNAREC] too)ptitSeb2024-08-101-2/+18
* Added 64bits 67 F3 0F 7F opcode ([ARM64_DYNAREC] too)ptitSeb2024-08-101-0/+6
* [INTERP] Fixed some undefined behaviour (#1717)Yang Liu2024-08-081-6/+12
* Small optimisation on xsave / xrstor helperptitSeb2024-08-071-12/+6
* Added 3 syscallsptitSeb2024-07-301-0/+3
* Added 67 66 0F EF opcode ([ARM64_DYNAREC] too)ptitSeb2024-07-231-1/+9
* Added 67 66 0F FE opcode ([ARM64_DYNAREC] too)ptitSeb2024-07-231-0/+10
* Improved exception/int 3 handlingptitSeb2024-07-212-4/+16
* Improved TF handlingptitSeb2024-07-211-2/+3
* [INTERPRETER] Fixed some issue with INT opcodes and STEP logicptitSeb2024-07-171-3/+3
* [TRACE] Fixed some issue with function name printingptitSeb2024-07-131-1/+4
* Added 1 syscall (for #1672)ptitSeb2024-07-121-0/+1
* fix some spelling (#1668)josch2024-07-101-2/+2
* Fixes (#1659)rajdakin2024-07-0918-190/+190
* [INTERPRETER] Added 64 66 8D opcode (#1648)Haichen Wu2024-07-062-3/+13
* Cosmetic changeptitSeb2024-07-041-3/+3
* Impl `sys_getpgrp` & `sys_getpgid` (#1637)Yip Coekjan2024-07-041-0/+4
* Handle `.relr.dyn` section (#1626)Yip Coekjan2024-07-021-1/+1
* [INTERPRETER] Added 64/65 F3 0F 58 opcodeptitSeb2024-06-251-0/+13
* [INTERPRETER] opcode F1 is valid alson in 64bitsptitSeb2024-06-241-4/+0
* [INTERPRETER] Added 32bits F1 opcodeptitSeb2024-06-241-0/+10
* Improved CPUID a bit more, adding RDRAND (helps geekbench6 avx2 version)ptitSeb2024-06-241-2/+18
* Fixed AVX.66.0F38 90-93 opcodes (certain special cases)ptitSeb2024-06-241-2/+2
* [TRACE] Print offset in function in hexptitSeb2024-06-231-1/+1
* Small improvment to 0F BC/BD opcodes ([ARM64_DYNAREC] too)ptitSeb2024-06-231-2/+2
* Added 66 F2/F3 A4 opcode ({DYNAREC] too)ptitSeb2024-06-221-1/+14
* [COSIM] Imprroved F2 0F prefixed opcodesptitSeb2024-06-222-25/+26
* [COSIM] Improved handling of AVX.66.0F38 3E/2F opcodesptitSeb2024-06-221-6/+16
* [TRACE] Cosmetic change on ymm printoutptitSeb2024-06-181-1/+1
* [COSIM] Some improvment to avoid segfault in edge casesptitSeb2024-06-173-4/+4
* More work on RDTSC emulationptitSeb2024-06-131-1/+1
* [INTERPRETER] Added AVX.0F 77 256bits opcodeptitSeb2024-06-111-2/+8
* [COSIM] Fixed 66 48 xx type of opcodesptitSeb2024-06-091-2/+5
* Remove a warning on known unhandled arch_prctl commandsptitSeb2024-06-081-0/+13
* [INTERPRETER] Fixed AVX.66.0F 50 opcode not handling vex.lptitSeb2024-06-081-0/+5
* [INTERPRETER] Added suport for F16C extension (linked to AVX flag) ([ARM64_DY...ptitSeb2024-06-064-1/+138
* [INTERPRETER] Fixed VCMP opcode familly, that needs more cases on than con-ve...ptitSeb2024-06-054-55/+116
* [INTERPRETER] Fixed name in comment of an opcodeptitSeb2024-06-031-2/+2
* [INTERPRETER] Fixed name in comment of an opcodeptitSeb2024-06-031-1/+1
* [COSIM] Added more helpers to avoid segfault on rare casesptitSeb2024-06-034-8/+11
* [INTERPRETER] Fixed VZEROUPPER opcodeptitSeb2024-06-031-1/+1
* [INTERPRETER] Added missing FMA opcodes, and fixed some existing onesptitSeb2024-06-021-12/+156
* [INTERPRETER] Fixed opcode name in commentptitSeb2024-06-021-3/+3
* [COSIM] Fixed YMM handling in cosim, seems to work better nowptitSeb2024-06-023-1/+16
* [INTERPRETER] Small cosmetic changes on raz of ymmptitSeb2024-06-021-9/+9
* [COSIM] Improved reliability with AVX (but there is still something wrong there)ptitSeb2024-06-022-14/+15
* [INTERPRETER] Added FMA cpu extension (linked to BOX64_AVX=2)ptitSeb2024-06-021-0/+447
* [COSIM] Fixed issue with YMM printing on differenceptitSeb2024-06-021-1/+1
* [INTERPRETER] Small fixes for some rare case of AES with serc==destptitSeb2024-06-021-19/+19
* [INTERP] Rework on the 16b emulation for LA64 (#1547)Yang Liu2024-06-011-12/+31