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* [RV64_DYNAREC] Added CC (and NativeCall) opcode, and shuffle around some xFla...ptitSeb2023-03-156-24/+84
* [RV64_DYNAREC] Implemented a solutionfor the problematic F_OF flag (use F_OF2...ptitSeb2023-03-156-6/+68
* [RV64_DYNAREC] Added E8 CALL opcode, and fixed some issue with many macrosptitSeb2023-03-156-19/+329
* [RV64_DYNAREC] Added 80 /7 CMP opcode (#567)Yang Liu2023-03-154-11/+120
* [RV64_DYNAREC] Added C6 MOV opcode (#566)Yang Liu2023-03-151-0/+39
* [RV64_DYNAREC] Added 39 CMP opcode and some fixes (#565)Yang Liu2023-03-154-55/+119
* Added 66 0F 38 29 PCMPEQQ opcde ([ARM64_DYNAREC] too) (for #558)ptitSeb2023-03-142-0/+16
* [RV64_DYNAREC] Added {81,83} /0 ADD opcode (#564)xctan2023-03-144-1/+110
* [RV64_DYNAREC] Added 85 TEST opcode (#563)Yang Liu2023-03-143-2/+63
* [RV64_DYNAREC] Added C1 /7 SAR opcode (#559)xctan2023-03-144-4/+107
* [RV64_DYNAREC] Small optimization for 31 XOR opcode (#561)Yang Liu2023-03-141-6/+11
* [RV64_DYNAREC] Added 31 XOR opcode (#560)Yang Liu2023-03-144-18/+88
* [ARM64_DYNAREC] Small optim when putting 0 in a memory locationptitSeb2023-03-131-6/+14
* [ARM64_DYNAREC] Use STUR/LDUR when possible, plus some other small improvmentsptitSeb2023-03-1322-463/+590
* [ARM64_DYNAREC] Optimised double push/pop with stp/ldp opcodeptitSeb2023-03-133-11/+70
* [ARM64_DYNAREC] Removed child leftover, it's not implemented anymoreptitSeb2023-03-134-26/+0
* [RV64_DYNAREC] Removed child leftover, it's not implemented anymoreptitSeb2023-03-134-19/+0
* [RV64_DYNAREC] Some small optim to getedptitSeb2023-03-131-11/+34
* [RV64_DYNAREC] Fixed scratch register conflict for SUB (#556)Yang Liu2023-03-132-3/+3
* [RV64_DYNAREC] Added 1 more scratch register (it was already saved/restored)ptitSeb2023-03-131-0/+1
* [RV64_DYNAREC] Fixed rv64_epilog_fast, but it's not used for nowptitSeb2023-03-131-6/+13
* [RV64_DYNAREC] Added 8B MOV opcode (#555)xctan2023-03-132-0/+15
* [DYNAREC] Fixed missing X_PEND need at end of block for unimplemented opcodeptitSeb2023-03-131-1/+13
* [ARM64_DYNAREC] Added unimplemented handling of CRC32 opcode (to avoid stoppi...ptitSeb2023-03-131-0/+36
* [RV64_DYNAREC] Added (81/83) SUB opcode (#554)Yang Liu2023-03-133-42/+108
* [RV64_DYNAREC] Added 29 SUB opcode (#553)Yang Liu2023-03-135-15/+168
* Tried to optimize TLS fetchingptitSeb2023-03-124-18/+20
* Cleanup mutex wrappingptitSeb2023-03-124-70/+6
* [DYNAREC] Fix some potential issue in the next jump handlingptitSeb2023-03-121-5/+7
* [ARM64_DYNAREC] Added 66 0F 3A 0A opcodeptitSeb2023-03-121-1/+19
* [ARM64_DYNAREC] Added (F2/F3) A7 opcodeptitSeb2023-03-121-1/+39
* Expose POPCNT capability tooptitSeb2023-03-122-1/+2
* [ARM64_DYNAREC] Added 66 0F 3A 0E opcodeptitSeb2023-03-121-0/+36
* [ARM64_DYNAREC] Added F4 opcodeptitSeb2023-03-121-0/+11
* Added support for SSE4.1, and added a couple of opcode ([ARM64_DYNAREC] too)ptitSeb2023-03-125-2/+47
* [ARM64_DYNAREC] Fixed buildptitSeb2023-03-124-1/+32
* [DYNAREC] Some renaming for the sake of consistancyptitSeb2023-03-127-26/+12
* Rv64 dynarec (#550)ptitSeb2023-03-1233-54/+3624
* [DYNAREC] Small optim for 66 0F 6D opcodeptitSeb2023-03-111-1/+3
* [DYNAREC] Soma need FASTROUND disabled for it's physics engineptitSeb2023-03-111-0/+3
* Start of new dev. cycleptitSeb2023-03-111-1/+1
* Bumped to v0.2.2ptitSeb2023-03-101-1/+1
* Added 2 more wrapped function to libgnutls (for #210)ptitSeb2023-03-091-2/+5
* Added libresolv to libc for glibc2.34+ (might help #210)ptitSeb2023-03-091-1/+2
* [DYNAREC] Simplify arm64 lock fileYang Liu2023-03-101-32/+32
* [DYNAREC] More small fixes to arm64 lock fileptitSeb2023-03-091-12/+1
* [ARM64] Fixed a typo in arm64_lock_incif0Yang Liu2023-03-091-1/+1
* [DYNAREC] Fixed a nasty bug in loadCache/unloadCache of x87 regsptitSeb2023-03-082-4/+4
* [DYNAREC] Added BOX64_DYNAREC_FORWARD parameter, with a default value to 128 ...ptitSeb2023-03-075-3/+64
* Removed ONCE optim in gtkclassptitSeb2023-03-071-41/+0