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* [INTERP] Fixed edge-case for VPERM2[F/I]128 opcodesptitSeb2025-05-011-4/+4
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* [ARM_DYNAREC] Small improvments to VMASKMOVP[S/D] opcodesptitSeb2025-05-011-100/+63
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* [INTERP] VMASKMOVP[S/D] opcodes have no register only pathptitSeb2025-05-011-0/+8
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* [ARM64_DYNAREC] Cosmetic change to VGATHER[D/Q]P[D/S] opcodesptitSeb2025-04-301-2/+4
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* [ARM64_DYNAREC] Small rework on VFMAD*S[S/D] opcodesptitSeb2025-04-301-3/+6
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* [INTERP] Fixed another instruction name commentptitSeb2025-04-301-1/+1
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* [ARM64_DYNAREC] Small improvment to VPBROADCAST[B/W] opcodesptitSeb2025-04-301-20/+10
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* [INTERP] Improved NAN handling on VSUBPD opcodeptitSeb2025-04-301-0/+4
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* [ARM64_DYNAREC] Fixed a potential issue with (V)STMXCSR opcodesptitSeb2025-04-302-2/+2
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* [ARM64_DYNAREC] Add fastnan=0 handling in (V)SQRTSS opcodesptitSeb2025-04-303-3/+27
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* [INTERP] Improved NAN handling for some (V)SQRTS[S/D] opcodesptitSeb2025-04-304-2/+12
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* [INTERP] Improve NAN handling on SQRTPS opcodeptitSeb2025-04-301-2/+4
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* [ARM64_DYNAREC] Switched RSQRTPS to precise instead of aproximateptitSeb2025-04-291-1/+8
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* [INTERP] Improved (V)RSQRTSS opcodesptitSeb2025-04-292-3/+20
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* [ARM64_DYNAREC] Switched RPCPS opcode to precise 1/A instead of approximateptitSeb2025-04-291-1/+7
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* [ARM64_DYNAREC] Small optim on PTEST opcodeptitSeb2025-04-291-17/+21
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* [INTERP] Fixed some more instruction name commentsptitSeb2025-04-291-2/+2
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* [RV64_DYNAREC] Minor optim to 8 bit TEST opcode (#2583)Yang Liu2025-04-283-13/+18
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* [RV64_DYNAREC] Small optimization to LEA opcode (#2582)Yang Liu2025-04-283-8/+9
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* [ARM64_DYNAREC] Mostly cosmetic changes to SSE/AVX packed shift opcodesptitSeb2025-04-282-43/+37
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* [INTERP] Fixes and improvments to SSE/AVX packed shift opcodesptitSeb2025-04-283-84/+40
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* [RV64_DYNAREC] Optimized rv64 printer for pseudo and jump instructions (#2581)Yang Liu2025-04-281-7/+55
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* Show Dynarec architecture in version string (#2580)Yang Liu2025-04-283-34/+43
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* [RV64_DYNAREC] Minor adjustment to dynarec_missing=2 (#2578)Yang Liu2025-04-283-4/+4
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* [ARM64_DYNAREC] Small optim for PSIGN[B/W/D] opcodesptitSeb2025-04-272-33/+27
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* [ARM64_DYNAREC] Some work on UD flags on (66) F3 0F BC/BD opcodesptitSeb2025-04-272-16/+64
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* [ARM64_DYNAREC] More work on UD flags for (66) F3 0F BC/BD opcodesptitSeb2025-04-272-4/+60
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* [ARM64_DYNAREC] Minor fox to F6 /7 opcodeptitSeb2025-04-271-1/+1
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* [INTERP] More work on UD flagsptitSeb2025-04-275-13/+65
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* [INTERP] Fixed some potential issue with LOCK ADC/SBB on Dynarec buildptitSeb2025-04-271-15/+23
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* [INTERP] Added 66 F3 0F BC opcodeptitSeb2025-04-271-0/+33
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* [WRAPPER] Reworked libssh2 wrapping, to make it more completeptitSeb2025-04-277-7/+418
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* [ELFLOADER] Fixed an issue were fail to load a library might endup unloading ↵ptitSeb2025-04-271-6/+0
| | | | used libraries
* [ELFLOADER] Added lib loading/unloading logs to DLSYM_ERRORptitSeb2025-04-272-6/+13
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* [RCFILE] Fixed BOX64_ROLLING_LOG not being a boolean but an integer valueptitSeb2025-04-271-1/+1
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* [ARM64_DYNAREC] Refactored (V)PSHUFD opcodesptitSeb2025-04-262-111/+183
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* [INTERP] Cosmetic change to VPSHUFD opocdeptitSeb2025-04-261-1/+1
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* [WRAPPER] Fixed some potential sagfault on my_backtrace wrapped functionptitSeb2025-04-261-0/+6
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* [ARM64_DYNAREC] Allow shift with saturation on (V)PMULH(U)W because it will ↵ptitSeb2025-04-263-10/+5
| | | | never saturate
* [ARM64_DYNAREC] Small fix for edge cases on (V)PMULHUW opcodesptitSeb2025-04-263-8/+10
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* [WRAPPER] Added some missing function to wrapped libgio-2 (for #2575)ptitSeb2025-04-267-2/+34
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* [ARM64_DYNAREC] Fixed (rarely used) some edge case for (V)PMULHRSW opcode ↵ptitSeb2025-04-255-4/+67
| | | | (and improved tests)
* [ARM64_DYNAREC] Small optim on some 256bits VPMOV[S/Z]X* opcodesptitSeb2025-04-251-22/+14
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* [ARM64_DYNAREC] Allow bigger block to be builtptitSeb2025-04-252-3/+5
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* [ARM64_DYNAREC] Minor change, (V)PMOVMSKB is only valid on register, not memoryptitSeb2025-04-252-39/+47
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* [INTERP] Another fix for a opcode name in commentptitSeb2025-04-251-1/+1
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* [INTERP] Fixed a small issue where VPCMP[E/I]STRM would not wipe upper ↵ptitSeb2025-04-251-2/+2
| | | | 128bits of ymm0
* [ARM64_DYNAREC] Fixed a potential issue with PCMPEQQ opcodes, and many ↵ptitSeb2025-04-251-63/+63
| | | | missing space in instruction name
* [ARM64_DYNAREC] Improved and fixed software fallback for (V)PCLMULQDQ opcodesptitSeb2025-04-242-37/+24
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* [ARM64_DYNAREC] Some optimisation to some (V)(P)BLEND* opcodesptitSeb2025-04-242-63/+21
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