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authorChristian Krinitsin <mail@krinitsin.com>2025-07-03 07:27:52 +0000
committerChristian Krinitsin <mail@krinitsin.com>2025-07-03 07:27:52 +0000
commitd0c85e36e4de67af628d54e9ab577cc3fad7796a (patch)
treef8f784b0f04343b90516a338d6df81df3a85dfa2 /results/classifier/deepseek-2/output/hypervisor/1815078
parent7f4364274750eb8cb39a3e7493132fca1c01232e (diff)
downloademulator-bug-study-d0c85e36e4de67af628d54e9ab577cc3fad7796a.tar.gz
emulator-bug-study-d0c85e36e4de67af628d54e9ab577cc3fad7796a.zip
add deepseek and gemma results
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+
+Qemu 3.1.0 risc-v mie.MEIE
+
+Hello all,
+
+There is a bug in qemu for Risc-v, related to the mie register: when we try to set the MEIE bit (11) nothing is done, even when we are running at machine mode.
+
+Li   a0 , 1 << 11
+Csrs mie , a0
+
+And when we read mie it is as though nothing was done.
+
+Going through the qemu source code I was able to correct it: on file op_helper.c, line 94, the variable all_ints should be initialized with:
+
+uint64_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP | MIP_MEIP;
+
+That is, the MIP_MEIP was missing.
+
+I've successfully triggered uart interrupts with this patch (virt machine).
+
+All the best,
+Pharos team
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