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| author | Richard Henderson <rth@twiddle.net> | 2016-12-27 14:59:24 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-12-27 14:59:24 +0000 |
| commit | 0a97c40f8e7172ac3d8db97fb22d0ef3025de307 (patch) | |
| tree | c8921d2662ee04a084d48311598a73c520e8ab0f | |
| parent | 416d72b97b01d6cb769ad0fd0e10614583354a45 (diff) | |
| download | focaccia-qemu-0a97c40f8e7172ac3d8db97fb22d0ef3025de307.tar.gz focaccia-qemu-0a97c40f8e7172ac3d8db97fb22d0ef3025de307.zip | |
target-arm: Fix aarch64 disas_ldst_single_struct
We add s->be_data within do_vec_ld/st. Adding it here means that we have the wrong bits set in SIZE for a big-endian host, leading to g_assert_not_reached in write_vec_element and read_vec_element. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1481085020-2614-3-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/translate-a64.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ef7601b5e6..f673d939e1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2830,9 +2830,9 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } else { /* Load/store one element per register */ if (is_load) { - do_vec_ld(s, rt, index, tcg_addr, s->be_data + scale); + do_vec_ld(s, rt, index, tcg_addr, scale); } else { - do_vec_st(s, rt, index, tcg_addr, s->be_data + scale); + do_vec_st(s, rt, index, tcg_addr, scale); } } tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); |