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| author | Alistair Francis <Alistair.Francis@wdc.com> | 2019-04-20 02:27:43 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-24 12:09:25 -0700 |
| commit | e06431108b0b1ef6ca76398d2b0b792ea24ae6bc (patch) | |
| tree | 57d37d6336ec270a9692f9a3478ea91fe6d55fc5 | |
| parent | d28b15a4d3b1e000ec7bf9090fe870cbc5f1eb2c (diff) | |
| download | focaccia-qemu-e06431108b0b1ef6ca76398d2b0b792ea24ae6bc.tar.gz focaccia-qemu-e06431108b0b1ef6ca76398d2b0b792ea24ae6bc.zip | |
target/riscv: Add the HGATP register masks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| -rw-r--r-- | target/riscv/cpu_bits.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a179137bc1..dc9d53d4be 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -208,6 +208,17 @@ #define CSR_HIDELEG 0xa03 #define CSR_HGATP 0xa80 +#if defined(TARGET_RISCV32) +#define HGATP_MODE SATP32_MODE +#define HGATP_ASID SATP32_ASID +#define HGATP_PPN SATP32_PPN +#endif +#if defined(TARGET_RISCV64) +#define HGATP_MODE SATP64_MODE +#define HGATP_ASID SATP64_ASID +#define HGATP_PPN SATP64_PPN +#endif + /* Performance Counters */ #define CSR_MHPMCOUNTER3 0xb03 #define CSR_MHPMCOUNTER4 0xb04 |