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authorNikita Shubin <n.shubin@yadro.com>2023-08-08 12:09:14 +0300
committerAlistair Francis <alistair.francis@wdc.com>2023-09-11 11:45:55 +1000
commite7a03409f29e2da59297d55afbaec98c96e43e3a (patch)
tree78cb871dd9b09ce2a3333deae689718dfd2fd808 /hw/arm/virt.c
parent4df282335b3b13db30123fbcca050e4bf690a9d9 (diff)
downloadfocaccia-qemu-e7a03409f29e2da59297d55afbaec98c96e43e3a.tar.gz
focaccia-qemu-e7a03409f29e2da59297d55afbaec98c96e43e3a.zip
target/riscv: don't read CSR in riscv_csrrw_do64
As per ISA:

"For CSRRWI, if rd=x0, then the instruction shall not read the CSR and
shall not cause any of the side effects that might occur on a CSR read."

trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls
riscv_csrrw_do64(), via helper_csrw() passing NULL as *ret_value.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230808090914.17634-1-nikita.shubin@maquefel.me>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/arm/virt.c')
0 files changed, 0 insertions, 0 deletions