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| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:07:19 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | 3471ae96b10bc0a1efeeeff85aea7a823cb57f77 (patch) | |
| tree | 159baf8b7c50776172699af73ee929153841f5bc /hw/arm/xlnx-versal.c | |
| parent | a23e719ca8e80d22eafe4b2b57833918d439fa0c (diff) | |
| download | focaccia-qemu-3471ae96b10bc0a1efeeeff85aea7a823cb57f77.tar.gz focaccia-qemu-3471ae96b10bc0a1efeeeff85aea7a823cb57f77.zip | |
hw/arm/xlnx-versal: split the xlnx-versal type
Split the xlnx-versal device into two classes, a base, abstract class and the existing concrete one. Introduce a VersalVersion type that will be used across several device models when versal2 implementation is added. This is in preparation for versal2 implementation. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-2-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/xlnx-versal.c')
| -rw-r--r-- | hw/arm/xlnx-versal.c | 31 |
1 files changed, 24 insertions, 7 deletions
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index a42b9e7140..4da656318f 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -2,6 +2,7 @@ * Xilinx Versal SoC model. * * Copyright (c) 2018 Xilinx Inc. + * Copyright (c) 2025 Advanced Micro Devices, Inc. * Written by Edgar E. Iglesias * * This program is free software; you can redistribute it and/or modify @@ -920,7 +921,7 @@ static void versal_unimp(Versal *s) static void versal_realize(DeviceState *dev, Error **errp) { - Versal *s = XLNX_VERSAL(dev); + Versal *s = XLNX_VERSAL_BASE(dev); qemu_irq pic[XLNX_VERSAL_NR_IRQS]; versal_create_apu_cpus(s); @@ -955,9 +956,9 @@ static void versal_realize(DeviceState *dev, Error **errp) &s->lpd.rpu.mr_ps_alias, 0); } -static void versal_init(Object *obj) +static void versal_base_init(Object *obj) { - Versal *s = XLNX_VERSAL(obj); + Versal *s = XLNX_VERSAL_BASE(obj); memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); @@ -975,7 +976,7 @@ static const Property versal_properties[] = { TYPE_CAN_BUS, CanBusState *), }; -static void versal_class_init(ObjectClass *klass, const void *data) +static void versal_base_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -984,16 +985,32 @@ static void versal_class_init(ObjectClass *klass, const void *data) /* No VMSD since we haven't got any top-level SoC state to save. */ } -static const TypeInfo versal_info = { - .name = TYPE_XLNX_VERSAL, +static void versal_class_init(ObjectClass *klass, const void *data) +{ + VersalClass *vc = XLNX_VERSAL_BASE_CLASS(klass); + + vc->version = VERSAL_VER_VERSAL; +} + +static const TypeInfo versal_base_info = { + .name = TYPE_XLNX_VERSAL_BASE, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(Versal), - .instance_init = versal_init, + .instance_init = versal_base_init, + .class_init = versal_base_class_init, + .class_size = sizeof(VersalClass), + .abstract = true, +}; + +static const TypeInfo versal_info = { + .name = TYPE_XLNX_VERSAL, + .parent = TYPE_XLNX_VERSAL_BASE, .class_init = versal_class_init, }; static void versal_register_types(void) { + type_register_static(&versal_base_info); type_register_static(&versal_info); } |