diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2025-09-06 06:09:44 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-09-24 10:29:43 -0700 |
| commit | 84142184899322c2dca931e36abca7a35a2827cd (patch) | |
| tree | d90f55e1a584e609f752b827f298f3aaf6d46513 /hw/core/cpu-system.c | |
| parent | b773c149a80b11449899b6a4ad3672250d4fcb0f (diff) | |
| download | focaccia-qemu-84142184899322c2dca931e36abca7a35a2827cd.tar.gz focaccia-qemu-84142184899322c2dca931e36abca7a35a2827cd.zip | |
accel/tcg: Move post-load tb_flush to vm_change_state hook
We need not call tb_flush once per cpu, only once per vmload. By moving the call from cpu_common_post_load to a tcg-specific vm_change_state_handler, we do even better than that: we only flush when called from HMP triggered loadvm, when we had old state to flush. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/core/cpu-system.c')
| -rw-r--r-- | hw/core/cpu-system.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 09c928c1f9..f601a083d1 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -23,7 +23,6 @@ #include "system/address-spaces.h" #include "exec/cputlb.h" #include "system/memory.h" -#include "exec/tb-flush.h" #include "qemu/target-info.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" @@ -207,14 +206,6 @@ static int cpu_common_post_load(void *opaque, int version_id) cpu_reset_interrupt(cpu, 0x01); tlb_flush(cpu); - - /* - * loadvm has just updated the content of RAM, bypassing the - * usual mechanisms that ensure we flush TBs for writes to - * memory we've translated code from. So we must flush all TBs, - * which will now be stale. - */ - tb_flush(cpu); } return 0; |