diff options
| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-08-17 15:57:57 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2022-08-17 13:08:11 -0400 |
| commit | 29d1fbc6c6ff04492fc67626aec5ebf2439739d0 (patch) | |
| tree | 6af98026dd6998af3ad067db0a1d63cef524e3d6 /hw/cxl/cxl-device-utils.c | |
| parent | d2289b524e71970ea8ca5602f219cc92b8e5896b (diff) | |
| download | focaccia-qemu-29d1fbc6c6ff04492fc67626aec5ebf2439739d0.tar.gz focaccia-qemu-29d1fbc6c6ff04492fc67626aec5ebf2439739d0.zip | |
hw/cxl: Add stub write function for RO MemoryRegionOps entries.
There is no checking on the availability of a write callback.
Hence QEMU crashes if a write does occur to one of these regions.
Discovered whilst chasing a Linux kernel bug that incorrectly
wrote into one of these regions.
Fixes: 6364adacdf ("hw/cxl/device: Implement the CAP array (8.2.8.1-2)")
Reported-by: Bobo WL <lmw.bobo@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220817145759.32603-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/cxl/cxl-device-utils.c')
| -rw-r--r-- | hw/cxl/cxl-device-utils.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c index 687759b301..83ce7a8270 100644 --- a/hw/cxl/cxl-device-utils.c +++ b/hw/cxl/cxl-device-utils.c @@ -141,9 +141,15 @@ static uint64_t mdev_reg_read(void *opaque, hwaddr offset, unsigned size) return retval; } +static void ro_reg_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + /* Many register sets are read only */ +} + static const MemoryRegionOps mdev_ops = { .read = mdev_reg_read, - .write = NULL, /* memory device register is read only */ + .write = ro_reg_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 1, @@ -173,7 +179,7 @@ static const MemoryRegionOps mailbox_ops = { static const MemoryRegionOps dev_ops = { .read = dev_reg_read, - .write = NULL, /* status register is read only */ + .write = ro_reg_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 1, @@ -188,7 +194,7 @@ static const MemoryRegionOps dev_ops = { static const MemoryRegionOps caps_ops = { .read = caps_reg_read, - .write = NULL, /* caps registers are read only */ + .write = ro_reg_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 1, |