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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-04-26 16:38:04 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-04-26 16:38:04 +0100 |
| commit | db7f1c3fafa8e1d23ecb212454f9d83ac59e411b (patch) | |
| tree | 413099fcac62061e19ba53ca49374d6394751a05 /hw/i386/intel_iommu.c | |
| parent | 06e64339555096a2bc2d08c7e012b36a9977062c (diff) | |
| parent | a4e0b436f44a4bb47ed4a75b0c05d2547cf12b1c (diff) | |
| download | focaccia-qemu-db7f1c3fafa8e1d23ecb212454f9d83ac59e411b.tar.gz focaccia-qemu-db7f1c3fafa8e1d23ecb212454f9d83ac59e411b.zip | |
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging
x86 queue, 2019-04-25 * Hygon Dhyana CPU model (Pu Wen) * Categorize a few devices in hw/i386 (Ernest Esene) * Support host-cache-info on TOPOEXT CPUID leaf (Stanislav Lanci) # gpg: Signature made Thu 25 Apr 2019 19:12:25 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: Pass through cache information for TOPOEXT CPUs Categorize devices: iommu Categorize devices: IGD passthrough ISA bridge i386: Add new Hygon 'Dhyana' CPU model Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/i386/intel_iommu.c')
| -rw-r--r-- | hw/i386/intel_iommu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2558f48fe6..44b1231157 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3741,6 +3741,8 @@ static void vtd_class_init(ObjectClass *klass, void *data) x86_class->int_remap = vtd_int_remap; /* Supported by the pc-q35-* machine types */ dc->user_creatable = true; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->desc = "Intel IOMMU (VT-d) DMA Remapping device"; } static const TypeInfo vtd_info = { |