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| author | Qi, Yadong <yadong.qi@intel.com> | 2019-11-25 08:33:21 +0800 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2019-11-25 03:42:58 -0500 |
| commit | e48929c787ed0ebed87877c97ac90c3a47ef7dda (patch) | |
| tree | 7894d1ab27d7efbb28dabe48063a3d2f764cf888 /hw/i386/intel_iommu.c | |
| parent | ce586f3b8d2105657981a1a43107fe7c5374b280 (diff) | |
| download | focaccia-qemu-e48929c787ed0ebed87877c97ac90c3a47ef7dda.tar.gz focaccia-qemu-e48929c787ed0ebed87877c97ac90c3a47ef7dda.zip | |
intel_iommu: TM field should not be in reserved bits
When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi <qi1.zhang@intel.com> Signed-off-by: Qi, Yadong <yadong.qi@intel.com> Message-Id: <20191125003321.5669-3-yadong.qi@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/i386/intel_iommu.c')
| -rw-r--r-- | hw/i386/intel_iommu.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index feb9e55f87..43c94b993b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3554,13 +3554,16 @@ static void vtd_init(IntelIOMMUState *s) * Rsvd field masks for spte */ vtd_spte_rsvd[0] = ~0ULL; - vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supported); vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supported); + vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supported); if (x86_iommu_ir_supported(x86_iommu)) { s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV; |