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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-05-24 10:16:29 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-05-24 10:16:29 +0100 |
| commit | ceac83e9ba724d915353d740a11ca08670deea59 (patch) | |
| tree | decd96395ed9a088790fafd0b503821264e5e5c9 /hw/intc/arm_gicv3_cpuif.c | |
| parent | 8dc7fd56dd4f56ab8ff1df3765ae6b5d3ac11c5e (diff) | |
| parent | 98e4f4fdb8ea05d840f51f47125924c2bb9df2df (diff) | |
| download | focaccia-qemu-ceac83e9ba724d915353d740a11ca08670deea59.tar.gz focaccia-qemu-ceac83e9ba724d915353d740a11ca08670deea59.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190523' into staging
target-arm queue:
* exynos4210: QOM'ify the Exynos4210 SoC
* exynos4210: Add DMA support for the Exynos4210
* arm_gicv3: Fix writes to ICC_CTLR_EL3
* arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
* target/arm: Fix vector operation segfault
* target/arm: Minor improvements to BFXIL, EXTR
# gpg: Signature made Thu 23 May 2019 15:22:55 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190523:
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
hw/arm/exynos4210: Add DMA support for the Exynos4210
hw/arm/exynos4: Use the IEC binary prefix definitions
hw/arm/exynos4: Remove unuseful debug code
hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
arm: Rename hw/arm/arm.h to hw/arm/boot.h
arm: Remove unnecessary includes of hw/arm/arm.h
arm: Move system_clock_scale to armv7m_systick.h
target/arm: Fix vector operation segfault
target/arm: Simplify BFXIL expansion
target/arm: Use extract2 for EXTR
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/arm_gicv3_cpuif.c')
| -rw-r--r-- | hw/intc/arm_gicv3_cpuif.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index cbad6037f1..3b212d91c8 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1856,7 +1856,7 @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value); /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */ - cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); + cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) { cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; } @@ -1864,7 +1864,7 @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR; } - cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); + cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); if (value & ICC_CTLR_EL3_EOIMODE_EL1S) { cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE; } @@ -2366,7 +2366,7 @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* Enforce "writing BPRs to less than minimum sets them to the minimum" * by reading and writing back the fields. */ - write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0)); + write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0)); write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1)); gicv3_cpuif_virt_update(cs); |