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path: root/hw/intc/arm_gicv3_cpuif.c (follow)
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* hw/intc/arm_gicv3: Introduce a 'first-cpu-index' propertyFrancisco Iglesias2025-10-071-1/+1
* target/arm: Drop define_one_arm_cp_reg_with_opaqueRichard Henderson2025-09-251-9/+1
* cleanup: Drop pointless return at end of functionMarkus Armbruster2025-04-241-1/+0
* target/arm: Move arm_current_el() and arm_el_is_aa64() to internals.hPeter Maydell2025-03-141-0/+1
* hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64()Peter Maydell2025-02-201-3/+3
* hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3Peter Maydell2025-02-201-9/+0
* include: Rename sysemu/ -> system/Philippe Mathieu-Daudé2024-12-201-2/+2
* hw/intc/arm_gicv3_cpuif: Add cast to match the documentationAlexandra Diupina2024-10-151-1/+1
* hw/intc/arm_gicv3: Add cast to match the documentationAlexandra Diupina2024-10-151-1/+1
* hw/intc/arm_gicv3: Add cast to match the documentationAlexandra Diupina2024-10-151-1/+1
* hw/intc/arm_gicv3: Report the VINMI interruptJinjie Ruan2024-04-251-2/+12
* hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()Jinjie Ruan2024-04-251-0/+4
* hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()Peter Maydell2024-04-251-12/+93
* hw/intc/arm_gicv3: Add NMI handling CPU interface registersPeter Maydell2024-04-251-5/+142
* hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabledPeter Maydell2024-04-021-2/+2
* hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registersPeter Maydell2024-01-091-0/+11
* hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registersPeter Maydell2024-01-091-4/+13
* system/cpus: rename qemu_mutex_lock_iothread() to bql_lock()Stefan Hajnoczi2024-01-081-1/+1
* hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZBen Dooks2023-11-201-2/+2
* target/arm: Mark up sysregs for HFGRTR bits 36..63Peter Maydell2023-02-031-0/+2
* hvf: arm: Add support for GICv3Alexander Graf2023-02-031-1/+15
* hw/intc/arm_gicv3: fix prio masking on pmr writeJens Wiklander2022-11-141-2/+1
* Fix 'writeable' typosPeter Maydell2022-06-081-1/+1
* hw/intc/arm_gicv3: Provide ich_num_aprs()Peter Maydell2022-05-191-6/+10
* hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell2022-05-191-4/+11
* hw/intc/arm_gicv3: Support configurable number of physical priority bitsPeter Maydell2022-05-191-54/+128
* hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1Peter Maydell2022-05-191-1/+1
* hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parametersPeter Maydell2022-05-191-5/+13
* target/arm: Replace sentinels with ARRAY_SIZE in cpregs.hRichard Henderson2022-05-051-5/+0
* target/arm: Split out cpregs.hRichard Henderson2022-05-051-0/+1
* hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell2022-04-221-1/+5
* hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarilyPeter Maydell2022-04-221-5/+5
* hw/intc/arm_gicv3_cpuif: Support vLPIsPeter Maydell2022-04-221-5/+114
* hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update()Peter Maydell2022-04-221-24/+40
* hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace eventPeter Maydell2022-03-071-1/+2
* hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.cPhilippe Mathieu-Daudé2021-12-151-9/+1
* gicv3: fix ICH_MISR's LRENP computationDamien Hedde2021-12-071-1/+2
* hw/intc/arm_gicv3: fix handling of LPIs in list registersPeter Maydell2021-11-291-3/+2
* hw/intc/arm_gicv3: Add new gicv3_intid_is_special() functionPeter Maydell2021-11-261-2/+2
* hw/intc: Set GIC maintenance interrupt level to only 0 or 1Shashi Mallela2021-09-201-2/+3
* hw/intc: GICv3 redistributor ITS processingShashi Mallela2021-09-131-2/+5
* hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_writeRicardo Koller2021-07-091-2/+2
* hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writesJean-Philippe Brucker2021-06-151-1/+4
* hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logicPeter Maydell2021-05-251-16/+32
* hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts workPeter Maydell2020-11-021-3/+2
* arm/gicv3: update virtual irq state after IAR register readJeff Kubascik2020-01-171-0/+3
* Include hw/irq.h a lot lessMarkus Armbruster2019-08-161-0/+1
* hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3Peter Maydell2019-05-231-2/+2
* hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}Peter Maydell2019-05-231-1/+1
* target/arm: Introduce arm_hcr_el2_effRichard Henderson2018-12-131-10/+11