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| author | Max Chou <max.chou@sifive.com> | 2025-09-23 17:07:28 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-10-03 13:15:14 +1000 |
| commit | ae4a37f57818e47e212272821a5a86ad54620eb8 (patch) | |
| tree | 9e068e7a815ac8f4ed31613154f1c227a26a9f15 /hw/intc/riscv_aplic.c | |
| parent | 0b16c7b6a854d461cdfd418769b51d58e43dd92a (diff) | |
| download | focaccia-qemu-ae4a37f57818e47e212272821a5a86ad54620eb8.tar.gz focaccia-qemu-ae4a37f57818e47e212272821a5a86ad54620eb8.zip | |
target/riscv: rvv: Replace checking V by checking Zve32x
The Zve32x extension will be applied by the V and Zve* extensions. Therefore we can replace the original V checking with Zve32x checking for both the V and Zve* extensions. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250923090729.1887406-2-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc/riscv_aplic.c')
0 files changed, 0 insertions, 0 deletions