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authorBALATON Zoltan <balaton@eik.bme.hu>2018-06-29 00:38:33 +0200
committerDavid Gibson <david@gibson.dropbear.id.au>2018-07-03 11:13:08 +1000
commit0123d3cbb06600e0624fdbf2255055d9cffe9c28 (patch)
tree96fe9f053b51e78a06a68132be7c85c03a555722 /hw/intc
parent2a8ceefca23bc2aaafe711f8afd7585be3c27064 (diff)
downloadfocaccia-qemu-0123d3cbb06600e0624fdbf2255055d9cffe9c28.tar.gz
focaccia-qemu-0123d3cbb06600e0624fdbf2255055d9cffe9c28.zip
target/ppc: Relax reserved bitmask of indexed store instructions
The PPC440 User Manual says that if bit 31 is set, the contents of
CR[CR0] are undefined for indexed store instructions but this form is
not invalid. Other PPC variants confirming to recent ISA where this
bit may be reserved should ignore reserved bits and not raise invalid
instruction exception. In particular, MorphOS has an stwx instruction
with bit 31 set and fails to boot currently because of this. With this
patch it gets further.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/intc')
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