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| author | Kane-Chen-AS <kane_chen@aspeedtech.com> | 2025-08-12 17:39:58 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-09-29 18:00:20 +0200 |
| commit | 688a3dae7828ca5ee6f45d510eed083420d72d8a (patch) | |
| tree | 5d0eaadaa2d119e3621fa4a4a1baa2d70c0966e1 /hw/misc/aspeed_sbc.c | |
| parent | 4975b64efb5aa4248cbc3760312bbe08d6e71638 (diff) | |
| download | focaccia-qemu-688a3dae7828ca5ee6f45d510eed083420d72d8a.tar.gz focaccia-qemu-688a3dae7828ca5ee6f45d510eed083420d72d8a.zip | |
hw/nvram/aspeed_otp: Add ASPEED OTP memory device model
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP) memory. This model simulates a word-addressable OTP region used for secure fuse storage. The OTP memory can operate with an internal memory buffer. The OTP model provides a memory-like interface through a dedicated AddressSpace, allowing other device models (e.g., SBC) to issue transactions as if accessing a memory-mapped region. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-2-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw/misc/aspeed_sbc.c')
0 files changed, 0 insertions, 0 deletions