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| author | Kane-Chen-AS <kane_chen@aspeedtech.com> | 2025-08-12 17:40:00 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-09-29 18:00:20 +0200 |
| commit | fe4159cb34f36a63a1759b907f51f8d458f5c940 (patch) | |
| tree | 013449c5d68bd527c6efa7898fa85c7c772b15ba /hw/misc/aspeed_sbc.c | |
| parent | 9f58dd0a8c30a6b84016db30949fe2f86f8bc38b (diff) | |
| download | focaccia-qemu-fe4159cb34f36a63a1759b907f51f8d458f5c940.tar.gz focaccia-qemu-fe4159cb34f36a63a1759b907f51f8d458f5c940.zip | |
hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs
The has_otp attribute is enabled in the SBC subclasses for AST2600 to control the presence of OTP support per SoC type. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-4-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw/misc/aspeed_sbc.c')
| -rw-r--r-- | hw/misc/aspeed_sbc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c index 46a038337c..b56a8b7678 100644 --- a/hw/misc/aspeed_sbc.c +++ b/hw/misc/aspeed_sbc.c @@ -273,8 +273,10 @@ static const TypeInfo aspeed_sbc_info = { static void aspeed_ast2600_sbc_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + AspeedSBCClass *sc = ASPEED_SBC_CLASS(klass); dc->desc = "AST2600 Secure Boot Controller"; + sc->has_otp = true; } static const TypeInfo aspeed_ast2600_sbc_info = { |