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| author | Arnaud Minier <arnaud.minier@telecom-paris.fr> | 2024-03-03 15:06:42 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-03-05 13:22:56 +0000 |
| commit | 60849fe4a79df0834c86aaa6669e1b64feb6150e (patch) | |
| tree | e562d6294377e446ae9aad2b3ef02dca5ac91def /include/hw/arm/stm32l4x5_soc.h | |
| parent | 3b551477172801bbfb78bf8f58c512307785fd9e (diff) | |
| download | focaccia-qemu-60849fe4a79df0834c86aaa6669e1b64feb6150e.tar.gz focaccia-qemu-60849fe4a79df0834c86aaa6669e1b64feb6150e.zip | |
hw/arm/stm32l4x5_soc.c: Use the RCC Sysclk
Now that we can generate reliable clock frequencies from the RCC, remove the hacky definition of the sysclk in the b_l475e_iot01a initialisation code and use the correct RCC clock. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240303140643.81957-8-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm/stm32l4x5_soc.h')
| -rw-r--r-- | include/hw/arm/stm32l4x5_soc.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h index 0b4f97e240..af67b089ef 100644 --- a/include/hw/arm/stm32l4x5_soc.h +++ b/include/hw/arm/stm32l4x5_soc.h @@ -54,9 +54,6 @@ struct Stm32l4x5SocState { MemoryRegion sram2; MemoryRegion flash; MemoryRegion flash_alias; - - Clock *sysclk; - Clock *refclk; }; struct Stm32l4x5SocClass { |