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authorSong Gao <gaosong@loongson.cn>2025-09-16 20:21:02 +0800
committerSong Gao <gaosong@loongson.cn>2025-09-28 17:31:04 +0800
commit4d4baab24179b51072f5e182aa41d44306ed593c (patch)
treed78882022d2787309898403d1d71a784acbf385b /include/hw/intc
parent86f4c80ab4a0d7a76d000515425d025004d6cd8b (diff)
downloadfocaccia-qemu-4d4baab24179b51072f5e182aa41d44306ed593c.tar.gz
focaccia-qemu-4d4baab24179b51072f5e182aa41d44306ed593c.zip
loongarch: add a direct interrupt controller device
Add Loongarch direct interrupt controller device base Definition.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20250916122109.749813-5-gaosong@loongson.cn>
Diffstat (limited to 'include/hw/intc')
-rw-r--r--include/hw/intc/loongarch_dintc.h35
1 files changed, 35 insertions, 0 deletions
diff --git a/include/hw/intc/loongarch_dintc.h b/include/hw/intc/loongarch_dintc.h
new file mode 100644
index 0000000000..aa94cd1003
--- /dev/null
+++ b/include/hw/intc/loongarch_dintc.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch  direct interrupt controller definitions
+ *
+ * Copyright (C) 2025 Loongson Technology Corporation Limited
+ */
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+#include "hw/loongarch/virt.h"
+
+
+#define NR_VECTORS     256
+
+#define TYPE_LOONGARCH_DINTC "loongarch_dintc"
+OBJECT_DECLARE_TYPE(LoongArchDINTCState, LoongArchDINTCClass, LOONGARCH_DINTC)
+
+typedef struct DINTCCore {
+    CPUState *cpu;
+    qemu_irq parent_irq;
+    uint64_t arch_id;
+} DINTCCore;
+
+struct LoongArchDINTCState {
+    SysBusDevice parent_obj;
+    DINTCCore *cpu;
+    uint32_t num_cpu;
+};
+
+struct LoongArchDINTCClass {
+    SysBusDeviceClass parent_class;
+
+    DeviceRealize parent_realize;
+    DeviceUnrealize parent_unrealize;
+};