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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2024-09-13 11:16:48 -0500 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-11-04 09:14:24 +1000 |
| commit | cebfeb9e56859bcac545a2340798e005cfde21cf (patch) | |
| tree | 178788ec38ab92f0e305143ee22cb5f79539c729 /include/hw/ppc/xive2.h | |
| parent | b9deafe7bf463fb7c7d7ee713774bfaf785eeb87 (diff) | |
| download | focaccia-qemu-cebfeb9e56859bcac545a2340798e005cfde21cf.tar.gz focaccia-qemu-cebfeb9e56859bcac545a2340798e005cfde21cf.zip | |
ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line"
Adds support for single byte writes to offset 0xC18 of the TIMA address space. When this offset is written to, the hardware disables the OS context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the OS CAM entry. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'include/hw/ppc/xive2.h')
| -rw-r--r-- | include/hw/ppc/xive2.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index ab68f8d157..654f485e9b 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -107,5 +107,7 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size); +void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size); #endif /* PPC_XIVE2_H */ |