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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-06-17 15:23:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-06-17 15:23:51 +0100 |
| commit | 227a8653669a8526dcef1020982628282f44820d (patch) | |
| tree | d9bd2ecaa4f7817f934e98056a7a770b35d6650a /include/hw/timer/aspeed_timer.h | |
| parent | b1a0eb777d9304ad69c577d5fdd8e20e4bf5644f (diff) | |
| download | focaccia-qemu-227a8653669a8526dcef1020982628282f44820d.tar.gz focaccia-qemu-227a8653669a8526dcef1020982628282f44820d.zip | |
hw/intc/arm_gicv3: Add IRQ handling CPU interface registers
Add the CPU interface registers which deal with acknowledging and dismissing interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-19-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/timer/aspeed_timer.h')
0 files changed, 0 insertions, 0 deletions