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| author | Nicholas Piggin <npiggin@gmail.com> | 2024-05-16 23:44:12 +1000 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-07-26 09:21:06 +1000 |
| commit | c8891955086b2fa795efb7fa0e409e32f25e5447 (patch) | |
| tree | 3ab5712de10e7371b2822a4c2f7f2c854a7763b3 /include | |
| parent | ca4f47752a14221a26cd2bf4710bb21ad2811a22 (diff) | |
| download | focaccia-qemu-c8891955086b2fa795efb7fa0e409e32f25e5447.tar.gz focaccia-qemu-c8891955086b2fa795efb7fa0e409e32f25e5447.zip | |
ppc/pnv: Implement POWER10 PC xscom registers for direct controls
The PC unit in the processor core contains xscom registers that provide low level status and control of the CPU. This implements "direct controls", sufficient for skiboot firmware, which uses it to send NMI IPIs between CPUs. POWER10 is sufficiently different from POWER9 (particularly with respect to QME and special wakeup) that it is not trivial to implement POWER9 support by reusing the code. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/ppc/pnv_core.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index c8784777a4..1de79a818e 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -109,6 +109,9 @@ OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD) struct PnvQuad { DeviceState parent_obj; + bool special_wakeup_done; + bool special_wakeup[4]; + uint32_t quad_id; MemoryRegion xscom_regs; MemoryRegion xscom_qme_regs; |