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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-16 12:09:08 +0100 |
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| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | d913c3992dfd9506a8201c2995d7c910a18db92f (patch) | |
| tree | a8fa3629ea6d29bd36d37f397ca722a46c9e688f /linux-user/mips/cpu_loop.c | |
| parent | 4d1524d2ce2f809ae514b23f8e9d502d051c6df4 (diff) | |
| download | focaccia-qemu-d913c3992dfd9506a8201c2995d7c910a18db92f.tar.gz focaccia-qemu-d913c3992dfd9506a8201c2995d7c910a18db92f.zip | |
target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-10-f4bug@amsat.org>
Diffstat (limited to 'linux-user/mips/cpu_loop.c')
0 files changed, 0 insertions, 0 deletions