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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-08-13 19:48:49 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-17 11:13:15 +0200 |
| commit | 4a367cfb00d3779f0113f871e4b7cb550d068098 (patch) | |
| tree | ae8eb92623098aee659a682571c97cb62191bd95 /python/qemu/console_socket.py | |
| parent | 90e22a57af975dea08b3015dfac072709f131616 (diff) | |
| download | focaccia-qemu-4a367cfb00d3779f0113f871e4b7cb550d068098.tar.gz focaccia-qemu-4a367cfb00d3779f0113f871e4b7cb550d068098.zip | |
target/mips/op_helper: Convert multiple if() to switch case
The cache operation is encoded in bits [20:18] of the instruction. The 'op' argument of helper_cache() contains the bits [20:16]. Extract the 3 bits and parse them using a switch case. This allow us to handle multiple cache types (the cache type is encoded in bits [17:16]). Previously the if() block was only checking the D-Cache (Primary Data or Unified Primary). Now we also handle the I-Cache (Primary Instruction), S-Cache (Secondary) and T-Cache (Terciary). Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20200813181527.22551-2-f4bug@amsat.org>
Diffstat (limited to 'python/qemu/console_socket.py')
0 files changed, 0 insertions, 0 deletions