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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-12 11:57:53 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-17 11:13:15 +0200 |
| commit | d0bec217ee0f6c948ba4579ca0f43a1a3f346cb4 (patch) | |
| tree | 2b7642eba94be8849c9089d67fe97200cbd42812 /python/qemu/console_socket.py | |
| parent | 68b981aa76079216f5765a6aecaf8728f27d3696 (diff) | |
| download | focaccia-qemu-d0bec217ee0f6c948ba4579ca0f43a1a3f346cb4.tar.gz focaccia-qemu-d0bec217ee0f6c948ba4579ca0f43a1a3f346cb4.zip | |
target/mips/cpu: Make cp0_count_rate a property
Since not all CPU implementations use a cores use a CP0 timer at half the frequency of the CPU, make this variable a property. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-11-f4bug@amsat.org>
Diffstat (limited to 'python/qemu/console_socket.py')
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