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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-05-05 23:38:36 +0200
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-06-24 16:44:14 +0200
commit2838b1d6356044eb240edd4e1b9b5ab5946c5b28 (patch)
tree0aa932192f6618fe303f58cef8d552df902c4b6d /python/qemu/utils/accel.py
parentd0ac9a61474cf594d19082bc8976247e984ea9a3 (diff)
downloadfocaccia-qemu-2838b1d6356044eb240edd4e1b9b5ab5946c5b28.tar.gz
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target/mips: Fix potential integer overflow (CID 1452921)
Use the BIT_ULL() macro to ensure we use 64-bit arithmetic.
This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN):

  CID 1452921:  Integer handling issues:

    Potentially overflowing expression "1 << w" with type "int"
    (32 bits, signed) is evaluated using 32-bit arithmetic, and
    then used in a context that expects an expression of type
    "uint64_t" (64 bits, unsigned).

Fixes: 074cfcb4dae ("target/mips: Implement hardware page table walker")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210505215119.1517465-1-f4bug@amsat.org>
Diffstat (limited to 'python/qemu/utils/accel.py')
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