diff options
| author | Fabiano Rosas <farosas@linux.ibm.com> | 2022-01-28 13:15:05 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-01-28 13:15:05 +0100 |
| commit | 35f579f5c21682311039f84e2e81254937e6ff78 (patch) | |
| tree | 91036c8f6e309c90cb732b3b54d29249388315bc /python/qemu/utils/accel.py | |
| parent | f9911e1e5513ebf661ae871ae31269a9a1cfabdc (diff) | |
| download | focaccia-qemu-35f579f5c21682311039f84e2e81254937e6ff78.tar.gz focaccia-qemu-35f579f5c21682311039f84e2e81254937e6ff78.zip | |
target/ppc: 405: Instruction storage interrupt cleanup
The 405 ISI does not set SRR1 with any exception syndrome bits, only a clean copy of the MSR. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg : Fixed removal which was done in the wrong routine ] Message-Id: <20220118184448.852996-13-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'python/qemu/utils/accel.py')
0 files changed, 0 insertions, 0 deletions