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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-17 13:15:55 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-21 17:12:50 +0100 |
| commit | 68245e442c9e5175d5e9d3a797dcab7eee800253 (patch) | |
| tree | 53d9ca79c7beaa1486d836b40e2f01b35aa98357 /python/qemu/utils/accel.py | |
| parent | ab59362fca0c23fbd21daceb78d6b2966fbf9793 (diff) | |
| download | focaccia-qemu-68245e442c9e5175d5e9d3a797dcab7eee800253.tar.gz focaccia-qemu-68245e442c9e5175d5e9d3a797dcab7eee800253.zip | |
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
Implement the MVE vector logical operations operating on two registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-12-peter.maydell@linaro.org
Diffstat (limited to 'python/qemu/utils/accel.py')
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