summary refs log tree commit diff stats
path: root/python
diff options
context:
space:
mode:
authorJiaxun Yang <jiaxun.yang@flygoat.com>2020-10-16 14:51:55 +0800
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-10-17 11:13:00 +0200
commitfd723105c15e09b8a9eaad29fa59347e63cfdb20 (patch)
treeb8f49093781196d0389af2541507d495999e1308 /python
parente10a0ca17dfeac25afb58f163b99d784b88d4e23 (diff)
downloadfocaccia-qemu-fd723105c15e09b8a9eaad29fa59347e63cfdb20.tar.gz
focaccia-qemu-fd723105c15e09b8a9eaad29fa59347e63cfdb20.zip
target/mips: Add loongson-ext lswc2 group of instructions (Part 2)
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.

This patch add implementation of these instructions:

  gslwlc1: similar to lwl but RT is FPR instead of GPR
  gslwrc1: similar to lwr but RT is FPR instead of GPR
  gsldlc1: similar to ldl but RT is FPR instead of GPR
  gsldrc1: similar to ldr but RT is FPR instead of GPR
  gsswlc1: similar to swl but RT is FPR instead of GPR
  gsswrc1: similar to swr but RT is FPR instead of GPR
  gssdlc1: similar to sdl but RT is FPR instead of GPR
  gssdrc1: similar to sdr but RT is FPR instead of GPR

Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <1602831120-3377-4-git-send-email-chenhc@lemote.com>
[PMD: Reuse t1 on MIPS32, reintroduce t2/fp0]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions