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| author | Kaiwen Xue <kaiwenx@rivosinc.com> | 2025-01-10 00:21:32 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:35 +1000 |
| commit | 5e33a20827150345350bede07e26a1bae320e682 (patch) | |
| tree | eb36b7bd5583b0114bb4332748e32540ac6d777a /rust/qemu-api/src | |
| parent | dbcb6e1ccf3f25292a8700bb18997a4411fad82f (diff) | |
| download | focaccia-qemu-5e33a20827150345350bede07e26a1bae320e682.tar.gz focaccia-qemu-5e33a20827150345350bede07e26a1bae320e682.zip | |
target/riscv: Support generic CSR indirect access
This adds the indirect access registers required by sscsrind/smcsrind and the operations on them. Note that xiselect and xireg are used for both AIA and sxcsrind, and the behavior of accessing them depends on whether each extension is enabled and the value stored in xiselect. Co-developed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-ID: <20250110-counter_delegation-v5-4-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'rust/qemu-api/src')
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