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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-06 13:02:32 -0500 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-09 11:47:54 +0100 |
| commit | da3d8b13624246702f7b8b88e37ee525a2f39ad2 (patch) | |
| tree | b73b1e9864b7a6ad035b94ae4b77d971cf31b580 /scripts/qapi/expr.py | |
| parent | 58e93b48aa1b9f0e6de7e57f6f68b6dda7a8198a (diff) | |
| download | focaccia-qemu-da3d8b13624246702f7b8b88e37ee525a2f39ad2.tar.gz focaccia-qemu-da3d8b13624246702f7b8b88e37ee525a2f39ad2.zip | |
target/arm: Enable SCR and HCR bits for RAS
Enable writes to the TERR and TEA bits when RAS is enabled. These bits are otherwise RES0. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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