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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-07-04 08:19:39 -0600 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-07-04 15:52:21 +0100 |
| commit | 3aad4bc8beb9a3a8c1ea3dc6ca9bfc85d3c7c8a4 (patch) | |
| tree | 5be64cfd336f61d16b1b9b467b64a8c3a30ac438 /target/arm/cpu.h | |
| parent | 694b2625dd4ac1d6f4aa4dfc8ed7380ec843cd9b (diff) | |
| download | focaccia-qemu-3aad4bc8beb9a3a8c1ea3dc6ca9bfc85d3c7c8a4.tar.gz focaccia-qemu-3aad4bc8beb9a3a8c1ea3dc6ca9bfc85d3c7c8a4.zip | |
target/arm: Add zt0_excp_el to DisasContext
Pipe the value through from SMCR_ELx through hflags and into the disassembly context. Enable EZT0 in smcr_write. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cbc2043483..39a9234ff2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1513,6 +1513,7 @@ FIELD(SVCR, ZA, 1, 1) /* Fields for SMCR_ELx. */ FIELD(SMCR, LEN, 0, 4) +FIELD(SMCR, EZT0, 30, 1) FIELD(SMCR, FA64, 31, 1) /* Write a new value to v7m.exception, thus transitioning into or out @@ -3084,6 +3085,7 @@ FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */ FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */ +FIELD(TBFLAG_A64, ZT0EXC_EL, 39, 2) /* * Helpers for using the above. Note that only the A64 accessors use |