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authorRichard Henderson <richard.henderson@linaro.org>2025-07-04 08:19:38 -0600
committerPeter Maydell <peter.maydell@linaro.org>2025-07-04 15:52:21 +0100
commit694b2625dd4ac1d6f4aa4dfc8ed7380ec843cd9b (patch)
tree612ee93d571db6cb055d98c065d0cc7100bf8ba3 /target/arm/cpu.h
parentd8ff459b4021a4fdbd3bf0c4311bb24868188f0d (diff)
downloadfocaccia-qemu-694b2625dd4ac1d6f4aa4dfc8ed7380ec843cd9b.tar.gz
focaccia-qemu-694b2625dd4ac1d6f4aa4dfc8ed7380ec843cd9b.zip
target/arm: Add ZT0
This is a 512-bit array introduced with SME2.
Save it only when ZA is in use.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250704142112.1018902-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c6041a9357..cbc2043483 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -716,6 +716,9 @@ typedef struct CPUArchState {
     uint64_t scxtnum_el[4];
 
     struct {
+        /* SME2 ZT0 -- 512 bit array, with data ordered like ARMVectorReg. */
+        uint64_t zt0[512 / 64] QEMU_ALIGNED(16);
+
         /*
          * SME ZA storage -- 256 x 256 byte array, with bytes in host
          * word order, as we do with vfp.zregs[].  This corresponds to