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| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-28 18:26:26 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-29 11:50:35 +0200 |
| commit | 30deb4605bf0bb4cc0682216002dfed738bd5700 (patch) | |
| tree | 7beaedf8c10b9797303587944521bb1774360a1c /target/mips/cpu.h | |
| parent | 1b142da5f82a8fcdc7783a418592de654d5c6052 (diff) | |
| download | focaccia-qemu-30deb4605bf0bb4cc0682216002dfed738bd5700.tar.gz focaccia-qemu-30deb4605bf0bb4cc0682216002dfed738bd5700.zip | |
target/mips: Clean up handling of CP0 register 1
Clean up handling of CP0 register 1. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-3-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 42d0e44e81..36e983a53f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -282,6 +282,14 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG00__MVPCONF1 3 #define CP0_REG00__VPCONTROL 4 /* CP0 Register 01 */ +#define CP0_REG01__RANDOM 0 +#define CP0_REG01__VPECONTROL 1 +#define CP0_REG01__VPECONF0 2 +#define CP0_REG01__VPECONF1 3 +#define CP0_REG01__YQMASK 4 +#define CP0_REG01__VPESCHEDULE 5 +#define CP0_REG01__VPESCHEFBACK 6 +#define CP0_REG01__VPEOPT 7 /* CP0 Register 02 */ #define CP0_REG02__ENTRYLO0 0 /* CP0 Register 03 */ |