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| author | Stafford Horne <shorne@gmail.com> | 2017-04-24 06:07:42 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-05-04 09:39:14 +0900 |
| commit | f4d1414a9385e3375d9107b29eeb75d27daf2147 (patch) | |
| tree | 91182987a6331fc44772a6179e170163b9635706 /target/openrisc/machine.c | |
| parent | 48a1b62baaf45e4d8d5ffac77647f7e898d7f7f1 (diff) | |
| download | focaccia-qemu-f4d1414a9385e3375d9107b29eeb75d27daf2147.tar.gz focaccia-qemu-f4d1414a9385e3375d9107b29eeb75d27daf2147.zip | |
target/openrisc: Support non-busy idle state using PMR SPR
The OpenRISC architecture has the Power Management Register (PMR) special purpose register to manage cpu power states. The interesting modes are: * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt * Suspend Model (SUME) - Stop cpu and all units - wake on reset The linux kernel will set DME when idle. This patch implements the PMR SPR and halts the qemu cpu when there is a change to DME or SME. This means that openrisc qemu in no longer peggs a host cpu at 100%. In order for this to work we need to kick the CPU when timers are expired. Update the cpu timer to kick the cpu upon each timer event. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/machine.c')
| -rw-r--r-- | target/openrisc/machine.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index a82be62466..a20cce705d 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -138,6 +138,7 @@ static const VMStateDescription vmstate_env = { VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), VMSTATE_UINT32(immucfgr, CPUOpenRISCState), VMSTATE_UINT32(evbar, CPUOpenRISCState), + VMSTATE_UINT32(pmr, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), |