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| author | Paolo Bonzini <pbonzini@redhat.com> | 2025-02-06 13:13:23 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-05-20 08:18:53 +0200 |
| commit | 5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4 (patch) | |
| tree | 36f5337db1d440bde02e71f98abac5bfc452925f /target/riscv/cpu.h | |
| parent | 71fb3aa5ebba5ba822371f864a12dbcded08147d (diff) | |
| download | focaccia-qemu-5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4.tar.gz focaccia-qemu-5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4.zip | |
target/riscv: store RISCVCPUDef struct directly in the class
Prepare for adding more fields to RISCVCPUDef and reading them in riscv_cpu_init: instead of storing the misa_mxl_max field in RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct and go through it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9de3f716ea..d2d4db95c1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -554,7 +554,7 @@ struct RISCVCPUClass { DeviceRealize parent_realize; ResettablePhases parent_phases; - RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + RISCVCPUDef *def; }; static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) |